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DESIGN ARCHITECTURE M2488 PRODUCT GUIDE
2-2 CG00000-011503 REV. A April 1997
2-3 OPERATION OF THE MAGNETIC TAPE CONTROLLER (MTC)
The DTC PCA contains all of the MTC (Magnetic Tape Controller) logic in a highly integrated imple-
mentation. This double-sided PCBA has extensive VLSI for reduced cost and increased reliability. The
M2488 uses one of four Interface Personality Modules (IPM) to configure the SCSI-2 interface for the
four combinations of wide or narrow and differential or single-ended operation.
The main functions contained on the DTC PCBA include:
1) Main Processor with all associated memory and support logic
2) Full SCSI-2 interface with RISC-based SCSI Protocol Controller (SPC)
3) 20 MB/s Host data path with EDRC logic
4) 2 MB Data Buffer
5) MTU (Formatter) digital read/write logic.
The processes performed by the DTC involve coordination of M2488 operation by the Main Processor
(CP):
- High-level SCSI I/F control of SPC
- Full control of data transfers on Host and MTU Data Paths
- Active Data Buffer management
- High-level control of MTU servo (tape motion)
Refer to the block diagram in Figure 2-2.
2-3.1 Data Path
The M2488 data path has been designed to allow data transfers up to a rate of 10Mbyte/s on a single
or two-byte wide SCSI interface and data transfers up to 20 Mbyte/s across a two-byte bus into the
controller buffer.
The SPC used is the Fujitsu MB86603 which is a fast and wide capable protocol controller intended
for high-performance systems. This controller operates in target mode and supports synchronous or
asynchronous data transfers. Performance enhancing features of the MB86603 are:
1) Programmable commands (512 bytes internal program memory).
2) Data FIFO register (64 bytes).
3) Automatic selection, reselection retry, and attention handling (e.g. combined sequences that
allow hardware to handle all SCSI protocols up through CDB acquisition).
4) Support of high-level commands.
Various data transfer rates can be set by programming the SPC internally from the default clock rate
of 20 MHz or an alternate 30 MHz clock.
2-3.2 Data Buffer
The remaining data path functions; host interface logic, host packet processor, buffer function con-
trol, and formatter packet processor; have been combined into a single data path LSI (SDDP). Buffer
performance has also been greatly enhanced. The SDDP buffer function control supports a three port
buffer with a 32 Mbyte/s bandwidth and 20 MHz clock. This allows 20 Mbyte/s data transfer rate on
the host port, up to 10 Mbyte/s burst transfers on the formatter port, and a microprocessor port over-
head up to 2 Mbyte/s. The host port is two bytes wide and the formatter port is a single byte wide.
The SDDP can support up to 8 Mbyte of buffer memory with a standard size of 2 Mbyte for the
M2488.
2-3.3 ERDC Compression Feature
Compression is performed by an improved design EDRC chip set prior to the data buffer. Placement
of compression before the buffer effectively extends buffer capacity by a factor equal to the average
compression rate. It also allows packet headers, which contain compression information for the entire