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CHAPTER 3 CPU
3.8 Overview of Instructions
The FR20 series supports logical operation and bit operations that are optimized for
embedded application, and direct addressing commands as well as a general RISC
command system. The set list shows the appendix. As each command is 16 bits length
(some commands are 32 or 48 bits), memory usage is more efficient.
■ Overview of Instructions
The instruction set can be divided into the following function groups.
• Arithmetic operation
• Load and store
•Divergence
• Logical operation and bit operation
• Direct addressing
•Others
●
Arithmetic operation
It has standard arithmetic operation commands (addition, subtraction, comparison) and shift commands
(logic shift, arithmetic operation shift). Operations with carry that are used for multi-word length operations
and operations that do not change the flag value which are convenient for address calculations are enabled
for addition and subtraction.
Furthermore, it has 32-bit x 32-bit and 16-bit x 16-bit multiplication commands, and the 32-bit/32-bit step
division commands.
Also equipped with an immediate transfer command that sets immediate values to the register, and an inter-
register transfer command.
The arithmetic operation command executes all operations using a general-purpose register and
multiplication/division register within the CPU.
●
Load and store
Load and store are the commands that read and write to external memories. They are also used to read and
write the peripheral circuits (I/O) within the chip.
Load and store have three types of access length, namely byte, half-word, and word. In addition to normal
indirect register memory addressing, memory addressing is also possible for certain commands such as
indirect displacement registers and indirect increment/decrement registers.
●
Branch
In the FR20 series, whether the operations are with or without delay slots can be specified for the branch
command.
It is an instruction of the branch, the call, the interruption, and the return. There are two types of branch
command. One type has a delay slot and the other does not. They can be optimized to suit the purpose.
Refer to "3.8.1 Branch Command with Delay Slot" and "3.8.2 Branch Command without Delay Slot" for