GE IC697VAL348 TV Converter Box User Manual


 
4-4 IC697VAL348 8-Channel, 16-bit Digital-to-Analog Converter Board User’s Manual GFK-2059
– December 2001
4
Delayed DAC Update Mode
In the DELAYED DAC UPDATE MODE, the processor sends the 16-bit word to be converted to
the first DAC register of the selected DAC. The data is stored there and transferred to the second
DAC register in one of two possible methods, described below.
Program Control Update Mode
One way for the transfer to occur is by writing a "one" to the Control Register bit D09. When the
data is transferred to the second register, digital-to-analog conversion begins and the analog output
settles to within 1/2 LSB in 10 µs. This method of updating the analog output is useful when more
than one DAC channel output is desired to change at a precise time. All eight DAC outputs could
be synchronized to change at certain periodic intervals under software control.
External Trigger Update Mode
The second method to update the second storage register and the DAC output by an external TTL
compatible trigger. This trigger must first have the external trigger circuitry enabled by installing
an on-board jumper as described in “Program Controlled and External Start Convert Mode” on
page 2-9. The PROGRAM CONTROL UPDATE MODE must also be enabled (refer to “Program
Controlled and External Start Convert Mode” on page 2-9). When the external trigger is received
(active low for a minimum of 150 ns), the value stored in the first DAC register will be transferred
to the second DAC register and begins a conversion. Using this method of updating, all
conversions can be synchronized to an external device.
Each of the DAC outputs may be multiplexed one at a time via the test MUX shown in Figure 4-3
on page 4-8. First, a control word must be written to the CSR to establish whether the analog output
is to be connected or disconnected from the P3 connector and which one of two test buses the
output is to be routed to. The DAC channel to be tested has test data written to it in the
IMMEDIATE UPDATE MODE. Address bits A01 through A04 are automatically latched into the
Address Register when the board is written to. The outputs of this Address Register select the DAC
channel that has just been updated via the test MUX. Test control information previously latched in
the CSRs passes the DAC output through the analog test switch to the test bus 2. Test bus 2 is
routed via the analog backplane (AMXbus™) to the input of the ADC board where it is available
for analog-to-digital conversion. When the ADC completes its conversion, it sends an end-of-
convert signal down the P2 backplane to the DAC. This signal removes either of the two test bus
outputs from the analog backplane. Along with the test bus 2 signal being sent to the ADC board
the analog ground (GND SEN) is switched out to the ADC board. This provides an input to the
ADC board, which is similar to a differential signal and is called pseudo-differential. Pseudo-
differential solves some of the associated common mode error problems with single-ended signals.
The input to the ADC board is referenced to the ground of the DAC board instead of the local
ground at the ADC board, effectively canceling out common mode errors associated with different
ground potentials at each of the boards.