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STK14C88-3
Document Number: 001-50592 Rev. ** Page 9 of 17
AC Switching Characteristics
SRAM Read Cycle
Parameter
Description
35 ns 45 ns
Unit
Min Max Min Max
Cypress
Parameter
Alt
t
ACE
t
ELQV
Chip Enable Access Time 35 45 ns
t
RC
[9]
t
AVAV,
t
ELEH
Read Cycle Time 35 45 ns
t
AA
[10]
t
AVQV
Address Access Time 35 45 ns
t
DOE
t
GLQV
Output Enable to Data Valid 15 20 ns
t
OHA
[10]
t
AXQX
Output Hold After Address Change 5 5 ns
t
LZCE
[11]
t
ELQX
Chip Enable to Output Active 5 5 ns
t
HZCE
[11]
t
EHQZ
Chip Disable to Output Inactive 13 15 ns
t
LZOE
[11]
t
GLQX
Output Enable to Output Active 0 0 ns
t
HZOE
[11]
t
GHQZ
Output Disable to Output Inactive 13 15 ns
t
PU
[8]
t
ELICCH
Chip Enable to Power Active 0 0 ns
t
PD
[8]
t
EHICCL
Chip Disable to Power Standby 35 45 ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled
[9, 10]
Figure 8. SRAM Read Cycle 2: CE and OE Controlled
[9]
W
5&
W
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W
5&
&(
W
$&(
W
/=&(
W
3'
W
+=&(
2(
W
'2(
W
/=2(
W
+=2(
'$7$9$/,'
$&7,9(
67$1'%<
W
38
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,&&
Notes
9. WE
and HSB must be HIGH during SRAM Read Cycles.
10.I/O state assumes CE
and OE < V
IL
and WE > V
IH
; device is continuously selected.
11. Measured ±200 mV from steady state output voltage.
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