132 EPSON S1C63000 CORE CPU MANUAL
CHAPTER 4: INSTRUCTION SET
SLL [%ir]
SLL [%ir]+ Shift left location [ir reg.] logical and increment ir reg. 2 cycles
Function: , ir ← ir + 1
Shifts the content of the data memory addressed by the ir register (X or Y) to the left for 1 bit.
Bit 3 of the r register moves to the C flag and bit 0 goes "0". Then increments the ir register (X
or Y). The increment result of the ir register does not affect the flags.
Code:
Mnemonic MSB LSB
SLL [%X]+ 100001110000110E1H
SLL [%Y]+ 100001110001110E3H
Flags: EICZ
↓ – ↕↕
Mode: Register indirect
Extended addressing: Invalid
Shift left location [ir reg.] logical 2 cycles
Function:
Shifts the content of the data memory addressed by the ir register (X or Y) to the left for 1 bit.
Bit 3 of the r register moves to the C flag and bit 0 goes "0".
Code:
Mnemonic MSB LSB
SLL [%X] 100001110000010E0H
SLL [%Y] 100001110001010E2H
Flags: EICZ
↓ – ↕↕
Mode: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: SLL [%X] Shifts the content of [00imm8] (00imm8 = 0000H + 00H to FFH)
LDB %EXT,imm8
SLL [%Y] Shifts the content of [FFimm8] (FFimm8 = FF00H + 00H to FFH)
[ir]
C
3210 0
[ir]
C
3210 0
