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Output Voltage Requirements
Notes:
1. VTT_PWRGD can be designed to be driving directly the OUTEN input.
2. Tb and Td voltage slopes are determined by soft start logic of the PWM controller.
3. Vboot is a default power-on Vcc (Core) value. Upon detection of a valid Vtt supply, the PWM controller is to
regulate to this value until the VID codes are read. The Vboot voltage is 1.1 V
4. VTT is the processor termination regulator’s output voltage and the VTT_PWRGD is the VTT regulator’s
power good status indicator.
5. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
6. This specification requires that the VID signals be sampled no earlier than 10 µs after VCC (at VCC_BOOT
voltage) and VTT are stable.
7. Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply
is in regulation as defined by the minimum and maximum DC/AC specifications for all components being
powered by it.
8. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor.
Measured between (0.3 * VTT) and (0.7 * VTT).
Figure 2-4. Power-On Sequence Timing Diagram
Vcc_CPU
VR_READY
RESET#
(for reference only)
VTT
V
BOOT
=1.1V
Te
V
CCPLL
(for reference only)
VID bits
/ BSEL[2:0]
Ta
BCLK [1:0]
(for reference only)
PWM Vcc
(5V/12V)
VTT_PWRGD
VID_SELECT
(pulled up to VTT)
OUTEN
Tf
Tc
Tb
Td
VID code read by PWM at the end of Tc
VID valid
CPU_PWGOOD (from platform, for reference only)
Tg
Table 2-5. Startup Sequence Timing Parameters (Sheet 1 of 2)
Timing Min Default Max Remarks
Ta =
PWM Vcc & Vtt to OUTEN delay
time
02.0 ms5.0 ms
If the actual timing exceeds 2ms, the
VTT VR must be capable of
supporting full Itt surge current
requirement per Proc’s latest EMTS
Tb =
Vboot rise time
0.05 ms
1
0.5 ms 10.0 ms
Programmable soft start ramp;
Measured from 10-90% of slope
Tc =
Vboot to VID valid delay time
0.05 ms
1
3.0 ms
