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SGH-I700 Block Diagrams
5-2
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2. SGH-i700 PDA Block Diagram
EtherN et
EtherN et
G eneral P urpose I/O
P X A 255
Flash
Memory
Flash
Memory
Dual Port
Memory
Dual Port
Memory
SDRAM
SDRAM
Memory
Controller
Variable
Latency I/O
Control
PC M CIA
& CF
Control
Dynamic
Memory
Control
Static
Memory
Control
Color or
Grayscale
LCD
Controller
Megacell
Core
System Bus
DM A Controller and Bridge
P eripheral Bus
RTC
OS Timer
PW M (2)
In t.
Controller
Clocks &
P ow er Man.
AC97
I2C
I2S
UART1
UART2
Fast IrD A
Slow IrD A
SSP
MMC
USB
Clien t
3.6864
MHz
Osc
32.768
KHz
Osc
LCD
Timing Controller
LCD
Timing Controller
W M 9705
W M 9705
IrD A
IrD A
UART
UART
USB
USB
Melody
Melody
SD Card
SD Card
C am era
C am era
Key Matrix
Key Matrix
JT A G
JT A G
JT A G
Test & D ubugging
EtherN et
EtherN et
G eneral P urpose I/O
P X A 255 P X A 255
Flash
Memory
Flash
Memory
Dual Port
Memory
Dual Port
Memory
SDRAM
SDRAM
Memory
Controller
Variable
Latency I/O
Control
PC M CIA
& CF
Control
Dynamic
Memory
Control
Static
Memory
Control
Color or
Grayscale
LCD
Controller
Megacell
Core
System Bus
DM A Controller and Bridge
P eripheral BusP eripheral Bus
RTC
OS Timer
PW M (2)
In t.
Controller
Clocks &
P ow er Man.
AC97
I2C
I2S
UART1
UART2
Fast IrD A
Slow IrD A
SSP
MMC
USB
Clien t
3.6864
MHz
Osc
32.768
KHz
Osc
LCD
Timing Controller
LCD
Timing Controller
W M 9705
W M 9705
IrD A
IrD A
UART
UART
USB
USB
Melody
Melody
SD Card
SD Card
C am era
C am era
Key Matrix
Key Matrix
SD Card
SD Card
C am era
C am era
Key Matrix
Key Matrix
JT A G
JT A G
JT A G
Test & D ubugging