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THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
D13_SPI_DO_M
D13_SPI_SCLK_M
D13_SPI_DI_M
D13_HDMI_TX0N
D13_HDMI_TX0P
D13_HDMI_TX1N
D13_HDMI_TX1P
D13_HDMI_TXCN
D13_HDMI_TXCP
D13_HDMI_TX2N
D13_HDMI_TX2P
D13_STPO_CLK
D13_STPO_SOP
D13_STPO_VAL
D13_STPO_ERR
D13_STPO_DATA
XTAL_OUT
XTAL_IN
R12007
1M
XTAL_OUT
XTAL_IN
SPI_DL_MODE
+3.3V_NORMAL
3.3K
R12016
D13_TDO_1
D13_TDI_1
P12000
12507WS-08L
1
2
3
4
5
6
7
8
9
+3.3V_NORMAL
D13_TRST_N_1
C12001
0.1uF
16V
R12004 33
R12003 33
R12002 33
R12000 33
R12001 33
D13_TCK_1
D13_TMS_1
D13_UART_RX_1
D13_UART_TX_1
P12001
12507WS-04L
1
2
3
4
5
+3.3V_NORMAL
R12006
33
R12005
33
C12002
0.1uF
16V
D13_SPI_CS/GPIO[0]
R12018
10K
OPT
R12015
0
1/16W
5%
D13_SPI_DO_M
D13_SPI_DI_M
C12005
0.1uF
D13_FLASH_WP
D13_SPI_SCLK_M
R12032
3.3K
R12017
10K
IC12001
MX25L3206EM2I-12G
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
R12019
33
+3.3V_NORMAL
D13_SPI_CS/GPIO[0]
R12010
10K
+3.3V_NORMAL
R12011
10K
OPT
D13_UART_RX_1
D13_UART_RX_0
D13_UART_TX_1
D13_UART_TX_0
D13_TMS_1
D13_TCK_0
D13_TCK_1
D13_TMS_0
D13_TDI_0
D13_TDI_1
D13_TRST_N_0
D13_TDO_0
D13_TRST_N_1
D13_TDO_1
R12027 33
R12026 33
R12025 33
SOC_SPI0_MOSI
SOC_SPI0_MISO
D13_TMS_0
D13_TDI_0
D13_TCK_0
D13_TRST_N_0
D13_TDO_0
D13_UART_TX_0
D13_UART_RX_0
R12037
1.6K1%
D13_HDMI_DDC_DA
D13_HDMI_HPD
D13_HDMI_DDC_CK
R12024 33
SOC_SPI0_SCLK
SOC_SPI0_CS0
R12028 33
OPT
R12030 33
OPT
I2C_SCL2
R12029 33
OPT
R12031 33
OPT
I2C_SDA2
D13_SPI_CS/GPIO[0]
C12004
0.01uF
D13_FLASH_WP
I2C_SDA2
D13_SPI_SCLK_M
R12046 0
+3.3V_NORMAL
R12039 0
I2C_SCL2
R12043
1K
R12038 0
D13_SPI_DI_M
R12042 0
P12002
12507WS-10L
1
2
3
4
5
6
7
8
9
10
11
R12044 0
OPT
R12040 0
R12047 0
R12041 0
SPI_DL_MODE
R12045 0
OPT
D13_SPI_CS/GPIO[0]
D13_SPI_DO_M
IC12000
LG1132-D13
IC_D13
XTALI
R2
XTALO
R1
PORES_N
A18
TRST_N0
E1
TMS0
C3
TCK0
D1
TDI0
B1
TDO0
D3
TRST_N1
E2
TMS1
B3
TCK1
D2
TDI1
B2
TDO1
C2
UART_RXD0
B10
UART_TXD0
A10
UART_RXD1
B9
UART_TXD1
A9
SPI_SCLK_S
C20
SPI_CS_S
D20
SPI_DO_S
D19
SPI_DI_S
C19
SPI_SCLK_M
A14
SPI_CS_M
B14
SPI_DO_M
B13
SPI_DI_M
A13
SCL_S
A11
SDA_S
B11
SCL_M
A12
SDA_M
B12
STPI_CLK
G20
STPI_SOP
H19
STPI_VAL
G19
STPI_ERR
H20
STPI_DATA[0]
J19
STPI_DATA[1]
J20
STPI_DATA[2]
K19
STPI_DATA[3]
K20
STPI_DATA[4]
L19
STPI_DATA[5]
L20
STPI_DATA[6]
M19
STPI_DATA[7]
M20
GPIO[7]
B7
GPIO[6]
A7
GPIO[5]
B6
GPIO[4]
A6
GPIO[3]
B5
GPIO[2]
A5
GPIO[1]
B4
GPIO[0]
A4
HDMI_DDC_CK
G1
HDMI_DDC_DA
G2
HDMI_HPD
J2
HDMI_REXT
J1
HDMI_CEC
H2
HDMI_DDCCEC
H1
HDMI_TX0N
M1
HDMI_TX0P
M2
HDMI_TX1N
L1
HDMI_TX1P
L2
HDMI_TX2N
K1
HDMI_TX2P
K2
HDMI_TXCN
N1
HDMI_TXCP
N2
SMODE[0]
F2
SMODE[1]
E3
TMODE[0]
A16
TMODE[1]
B16
TMODE[2]
A17
TMODE[3]
B17
D13_FLASH_WP
X12000
24.75MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
C12003
27pF
50V
C12000
27pF
50V
D13_RESET
R12008 33
R12012 33
R12022 33
R12023 33
R12033 33
C12261
10pF
R12014
33
D13_SMODE[0]
D13_SMODE[1]
R12013
10K
+3.3V_NORMAL
R12021
10K
R12009
10K
OPT
D13_SMODE[1]
+3.3V_NORMAL
D13_SMODE[0]
R12020
10K
OPT
+3.3V_NORMAL
R12034
3.3K
R12035
3.3K
R12036
3.3K
OPT
R12048
3.3K
D13_INT
R12049
10
33
R12050
R12051
33
XTAL(24.75MHz)
JTAG for HEVC
UART For HEVC
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
SPI FLASH(4MByte)
GPIO[0]
- 1 : Serial Flash Boot
- 0 : Live Boot
Closed to D13
Serial Flash Boot Test
HEVC option sheet
* Default Internal Pull-Up
SMODE[1:0]
- 00 : Normal Mode
- Other : Test Mode
H/W Option : default low
SPI Clock Frq. &
DDR density
(High:512MB, LOW:256MB)
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only