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3 SPECIFICATION
MELSEC-QnA
3.4 I/O Signals to the Programmable Controller CPU
The I/O signals for the master/local module's programmable controller CPU is
described.
3.4.1 I/O signal list
The list of I/O signals is described in Table 3.3.
The "n" in the table indicates the master/local module's first I/O number, and it is
determined by the installation position and the module installed before the master/local
module.
<Example> When the master/local module's first I/O number is "X/Y30":
Xn0 to X(n+1)F
X30 to X4F
Yn0 to Y(n+1)F
Y30 to Y4F
Table 3.3 I/O signal list
Signal direction: programmable controller CPU master/local module Signal direction: programmable controller CPU master/local module
Availability Availability
Input
number
Signal name
Master
station
Local
station
Output
number
Signal name
Master
station
Local
station
Xn0 Module error
Yn0 Refresh instruction
Xn1 Data link status at host station
Yn1
Xn2 Parameter setting status
Yn2
Xn3 Data link status at other stations
Yn3
(Prohibited to use) – –
Xn4 Module reset acceptance complete
Yn4 Module reset request
Xn5 (Prohibited to use) – – Yn5 (Prohibited to use) – –
Xn6
Data link startup by buffer memory
parameter normal completion
Yn6
Data link startup request from buffer
memory parameters
Xn7
Data link startup by buffer memory
parameter error completion
Yn7 (Prohibited to use) – –
Xn8
Data link startup by E
2
PROM
parameter normal completion
Yn8
Data link startup request from the
E
2
PROM parameters
Xn9
Data link startup by E
2
PROM
parameter error completion
Yn9 (Prohibited to use) – –
XnA
Parameter registration to E
2
PROM
normal completion
YnA
Parameter registration request to
E
2
PROM
XnB
Parameter registration to E
2
PROM
error completion
YnB
XnC (Prohibited to use) – – YnC
(Prohibited to use) – –
XnD
E
2
PROM erasure normal completion
YnD
E
2
PROM erasure request
XnE
E
2
PROM erasure abnormal
completion
YnE
XnF Module ready
YnF
(Prohibited to use) –
–
: Usable : Prohibited to use