Filter
Top Products
MAX5811
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
8 _______________________________________________________________________________________
a serial clock line (SCL). The MAX5811 is SMBus com-
patible within the range of V
DD
= 2.7V to 3.6V. SDA and
SCL facilitate bidirectional communication between the
MAX5811 and the master at rates up to 400kHz. Figure
1 shows the 2-wire interface timing diagram. The
MAX5811 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5811 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
by a START (S) or REPEATED START (S
r
) condition and
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
The MAX5811 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor (500Ω or greater) to
generate a logic high voltage (see Typical Operating
Circuit). Series resistors R
S
are optional. These series
resistors protect the input stages of the MAX5811 from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions). SDA and SCL idle high when the
I
2
C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
Figure 1. 2-Wire Serial lnterface Timing Diagram
SCL
SDA
STOP
CONDITION
START
CONDITION
REPEATED START CONDITIONSTART CONDITION
t
LOW
t
SU, DAT
t
SU, STA
t
SP
t
BUF
t
HD, STA
t
SU, STO
t
R
t
F
t
HD, STA
t
HIGH
t
HD, DAT
SCL
SDA
SS
r
P
Figure 2. START/STOP Conditions
Figure 3. Early STOP Condition
SCL
SDA
STOP START
SCL
SDA
ILLEGAL
STOP
START
ILLEGAL EARLY STOP CONDITION
LEGAL STOP CONDITION