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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 255
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.80
7.80 FMULs (Single Precision Floating Point Multiply)
FRk is multiplied by FRj, and its result is stored in FRi.
Assembler Format
FMULs FRk, FRj, FRi
Operation
FRk × FRj FRi
Classification
Single-precision floating point instruction, FR81 family
Execution Cycles
1 cycle
Instruction Format
EIT Occurrence and Detection
An invalid instruction exception (FPU absence error), an FPU exception, or an interrupt is detected.
MSB LSB
(n+0)0000011110100111
(n+2) - FRk FRj FRi