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FR81 Family
364 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.142
7.142 ORH (Or Halfword Data of Source Register to Data in
Memory)
Takes the logical OR if the half-word data at memory address Ri and the half-word data
in Rj, stores the results to the memory address corresponding to Ri.
● Assembler Format
ORH Rj,@Ri
● Operation
(Ri) | Rj → (Ri)
● Flag Change
N: Set when the MSB(bit15) of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is zero, cleared otherwise.
V, C: Unchanged.
● Classification
Logical Calculation instruction, Read/Modify/Write type instruction
● Execution Cycles
1+2a cycles
● Instruction Format
NZV C
CC - -
MSB LSB
10010101 Rj Ri