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MAX12527
Analog Inputs and Input Track-and-Hold
(T/H) Amplifier
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a V
DD
/ 2 common-mode input voltage.
The MAX12527 sampling clock controls the switched-
capacitor input T/H architecture (Figure 3) allowing the
analog input signals to be stored as charge on the
sampling capacitors. These switches are closed (track
mode) when the sampling clock is high and open (hold
mode) when the sampling clock is low (Figure 4). The
analog input signal source must be able to provide the
dynamic currents necessary to charge and discharge
the sampling capacitors. To avoid signal degradation,
these capacitors must be charged to one-half LSB
accuracy within one-half of a clock cycle. The analog
input of the MAX12527 supports differential or single-
ended input drive. For optimum performance with dif-
ferential inputs, balance the input impedance of IN_P
and IN_N and set the common-mode voltage to mid-
supply (V
DD
/ 2). The MAX12527 provides the optimum
common-mode voltage of V
DD
/ 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 9, 10, and 11.
Reference Output
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12527. The power-down logic input (PD) enables
and disables the reference circuit. REFOUT has approxi-
mately 17kΩ to GND when the MAX12527 is powered
down. The reference circuit requires 10ms to power up
and settle to its final value when power is applied to the
MAX12527 or when PD transitions from high to low.
The internal bandgap reference produces a buffered
reference voltage of 2.048V ±1% at the REFOUT pin
with a ±50ppm/°C temperature coefficient. Connect an
external ≥0.1µF bypass capacitor from REFOUT to
GND for stability. REFOUT sources up to 1mA and
sinks up to 0.1mA for external circuits with a 35mV/mA
load regulation. Short-circuit protection limits I
REFOUT
to a 2.1mA source current when shorted to GND and a
0.24mA sink current when shorted to V
DD
. Similar to
REFOUT, REFIN should be bypassed with a 4.7µF
capacitor to GND.
Reference Configurations
The MAX12527 full-scale analog input range is ±2/3 x
V
REF
with a V
DD
/ 2 ±0.5V common-mode input range.
V
REF
is the voltage difference between REFAP (REFBP)
and REFAN (REFBN). The MAX12527 provides three
modes of reference operation. The voltage at REFIN
(V
REFIN
) selects the reference operation mode (Table 1).
Connect REFOUT to REFIN either with a direct short or
through a resistive divider to enter internal reference
mode. COM_, REF_P, and REF_N are low-impedance
outputs with V
COM_
= V
DD
/ 2, V
REFP
= V
DD
/ 2 + 3/8 x
V
REFIN
, and V
REF_N
= V
DD
/ 2 - 3/8 x V
REFIN
. Bypass
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.
Dual, 65Msps, 12-Bit, IF/Baseband ADC
16 ______________________________________________________________________________________
V
REFIN
REFERENCE MODE
35% V
REFOUT
to 100%
V
REFOUT
Internal Reference Mode.
REFIN is driven by REFOUT either through a
direct short or a resistive divider.
V
COM_
= V
DD
/ 2
V
REF_P
= V
DD
/ 2 + 3/8 x V
REFIN
V
REF_N
= V
DD
/ 2 - 3/8 x V
REFIN
0.7V to 2.3V
Buffered External Reference Mode.
An external 0.7V to 2.3V reference voltage is
applied to REFIN.
V
COM_
= V
DD
/ 2
V
REF_P
= V
DD
/ 2 + 3/8 x V
REFIN
V
REF_N
= V
DD
/ 2 - 3/8 x V
REFIN
<0.5V
U nb uffer ed E xter nal Refer ence M od e.
RE F_P , RE F_N , and C O M _ ar e d r i ven b y
exter nal r efer ence sour ces. The ful l - scal e
anal og i np ut r ang e i s ± ( V
R E F _P
- V
R E F _N
) x 2/3.
Table 1. Reference Modes
MAX12527
C
PAR
2pF
V
DD
BOND WIRE
INDUCTANCE
1.5nH
IN_P
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*C
SAMPLE
4.5pF
C
PAR
2pF
V
DD
BOND WIRE
INDUCTANCE
1.5nH
IN_N
*C
SAMPLE
4.5pF
R
IN
=
1
f
CLK
x C
SAMPLE
Figure 3. Internal T/H Circuit