Fujitsu F2MCTM-16LX Manual

A SERVICE OF

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CHAPTER 15 WATCH TIMER

15.3 Configuration of Watch Timer

This section explains the registers and interrupt factors of the watch timer.

■ List of Registers and Reset Values of Watch Timer

Figure 15.3-1 List of Registers and Reset Values of Watch Timer

■ Generation of Interrupt Request from Watch Timer

• When the interval time set by the interval time select bits (WTC:WTC2 to WTC0) is reached, the

overflow flag bit (WTC:WTOF) is set to "1".

• When the overflow flag bit is set (WTC:WTOF = 1) with interrupt enabled when the watch timer

counter overflows (carries) (WTC:WTIE = 1), an interrupt request is generated.

10000

×

654321

01

70

bit

Address: 0000AA

H

✕: Undefined

Watch timer control register (WTC)