Philips DV29 DVD Player User Manual


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ISSUE
DRAWING NO.
DRAWING TITLE
DATE
Filename:
ECO No. DESCRIPTION OF CHANGE
L971C11.Sch
DV29 HDMI
Contact Engineer:
L971C11
24-Aug-2004
INITIALS
Printed:
11 11Sheet of
Notes:
Contact Tel: (01223) 203270Peter Gaggs
A & R Cambridge Ltd.
Pembroke Avenue
Cambridge CB5 9QR
Waterbeach

A2
+3V3D
L1103
120R@100MHz
C1103
100N
16V
0603
C1119
100UF
10V
YXF
C1106
100N
16V
0603
C1107
100N
16V
0603
DGND
3V3_AVCC
L1102
120R@100MHz
C1102
100N
16V
0603
C1118
100UF
10V
YXF
C1105
100N
16V
0603
DGND
3V3_PVCC1
C1123
1N0
50V
0603
L1101
120R@100MHz
C1101
100N
16V
0603
C1117
100UF
10V
YXF
C1104
100N
16V
0603
DGND
3V3_PVCC2
C1122
1N0
50V
0603
C1124
1N0
50V
0603
C1125
1N0
50V
0603
C1108
100N
16V
0603
C1109
100N
16V
0603
C1110
100N
16V
0603
C1120
100UF
10V
YXF
+3V3D
DGND
HDMI TX
+3V3
REG1100
LM1086CS-3.3
TO-263
C1116
10UF
50V
YK
C1100
100N
16V
0603
+5VD
DGND
HDMI_RESET*
HDMI_RESET*
+3V3D
9190_INT*
9190_INT*
SCL
SDA
SCL
SDA
OE
1
A0
2
Y0
18
A1
4
Y1
16
A2
6
Y2
14
A3
8
Y3
12
IC1100A
74LVC244APW
TSSOP-20
OE
1
A0
2
Y0
18
A1
4
Y1
16
A2
6
Y2
14
A3
8
Y3
12
IC1101A
74LVC244APW
TSSOP-20
OE
19
A0
17
Y0
3
A1
15
Y1
5
A2
13
Y2
7
A3
11
Y3
9
IC1100B
74LVC244APW
TSSOP-20
OE
19
A0
17
Y0
3
A1
15
Y1
5
A2
13
Y2
7
A3
11
Y3
9
IC1101B
74LVC244APW
TSSOP-20
VIDP[0..19]
VIDP[0..19]
DGND
VSYNC*
CLK27M_VID
MCLK_HDMI
SPDIF
VSYNC*
HSYNCD*
CLK27M_VID
MCLK_HDMI
SPDIF
PROG/INT*
1=Prog scan, 0=Interlaced
GND
10
VCC
20
IC1100C
74LVC244APW
TSSOP-20
GND
10
VCC
20
IC1101C
74LVC244APW
TSSOP-20
C1111
100N
16V
0603
C1112
100N
16V
0603
C1121
100UF
10V
YXF
+3V3D
DGND
VIDP9
VIDP8
VIDP7
VIDP6
VIDP5
VIDP4
VIDP3
VIDP2
VIDP1
VIDP0
VIDP11
VIDP10
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
VIDP19
VIDP18
VIDP17
VIDP16
VIDP15
VIDP14
VIDP13
VIDP12
VIDP7
VIDP6
VIDP5
VIDP4
VIDP3
VIDP2
VIDP1
VIDP0
VIDEO BUSES
1. Progressive Mode: 10 Bit Y/C on 20 bit wide bus
Vaddis V Output Function SiI9190 Input
VIDP19..12 Y9..2 D15..8
VIDP11..10 Y1..0 D3..2
VIDP9..2 C9..2 D23..16
VIDP1..0 C1..0 D7..6
(C = multiplexed CbCr data)
2. Interlaced Mode: 8 Bit multiplexed YCbCr
Vaddis V Output Function SiI9190 Input
VIDP7..0 YC7..0 D15..8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SCREEN
22
SCREEN
23
SCREEN
21
SCREEN
20
SKT1100
MOLEX
500254
EMC_GND
EMC_GND
Cable screen capacitively
coupled to chassis to avoid
connecting 0V to chassis via
external equipment
C1128
1N0
50V
0603
C1126
1N0
50V
0603
DGND
DGND
TX2+
DGND
TX2-
TX1+
TX1-
TX0+
TX0-
TXC+
TXC-
TR1101
MMUN2211LT1
SOT-23
DZ1100
BZX84C
5V6
SOT-23
C1127
1N0
50V
0603
TR1100
MMUN2211LT1
SOT-23
+3V3D
DGND
HOTPLUG buffer
HPD
HPDIN
2
+5
18
3
6
7
REG1101
L78L05ACD
SO-8
C1114
100N
16V
0603
C1115
100N
16V
0603
C1133
100UF
25V
YK
+12VD
DGND
+5V_HDMI
HDMI +5V Power Signal
D1100
BAT54S
SOT-23
R1112
100R
0W063
0603
L1104
120R@100MHz
+5VD
DGND
DGND
DDC_SCL
D1101
BAT54S
SOT-23
R1113
100R
0W063
0603
L1105
120R@100MHz
+5VD
DGND
DGND
DDC_SDA
DDC_SCL_OUT
DDC_SDA_OUT
To Vaddis
To Vaddis
L1100
120R@100MHz
NF
Option to bypass reg
+3V3D
3V3_AVCC
ADAT0
ADAT1
ADAT2
ALRCLK
ABCLK_HDMI
TR1102
MMUN2211LT1
SOT-23
DGND
+3V3D
D1102
BAT54S
SOT-23
R1116
100R
0W063
0603
L1106
120R@100MHz
+3V3D
DGND
DGND
CEC
To Vaddis
R1115
27K
0W063
0603
CEC_OUT
R1117
100R
0603
P1101
P1100
P1102
P1103
P1104
P1113P1112
P1110P1108
P1109P1107P1105
P1106
P1111
P1114
P1115
P1116
P1117
P1122
P1123
P1124
P1125
P1118
P1119
P1120
P1121
P1126
P1127
P1128
P1129
P1130
P1131
DGND
C1134
100N
16V
0603
C1135
100N
16V
0603
C1136
100N
16V
0603
C1137
100N
16V
0603
+3V3D
DGND
Around video bus
C1138
100N
16V
0603
R1109
1K0
0W125
0805
R1105
10K
0W125
0805
R1106
10K
0W125
0805
R1107
10K
0W125
0805
R1114
10K
0805
C1130
10N
50V
0603
C1129
10N
50V
0603
P1132
1 8
RP1100A
100R
2 7
RP1100B
100R
63
RP1100C
100R
54
RP1100D
100R
1 8
RP1101A
100R
2 7
RP1101B
100R
63
RP1101C
100R
54
RP1101D
100R
+3V3_HDMI
P1133
C1113
27P
100V
0805
C1131
27P
100V
0805
C1132
27P
100V
0805
+5VD
RESET#
42
INT
17
HPD
18
CSCL
43
CSDA
44
D23
49
D19
53
D18
54
D17
55
D16
56
D15
57
D14
58
D13
61
D12
62
D11
63
D10
64
D9
65
D8
67
D7
68
D6
69
D5
70
D4
75
D3
76
D2
77
D1
78
D0
79
D22
50
D21
51
D20
52
DE
80
VSYNC
2
HSYNC
1
IDCK
66
MCLK
6
SPDIF
5
RSVDL
21
PGND1
22
EXT_SWING
24
TX2-
35
TX2+
36
AVCC
28
AGND
25
PVCC1
23
TX1-
32
TX1+
33
TX0-
29
TX0+
30
TXC-
26
TXC+
27
AVCC
34
AGND
31
AGND
37
PGND2
39
PVCC2
38
IOVCC
13
IOGND
14
EPAD
SCK
12
WS
11
SD0
10
SD1
9
SD2
8
SD3
7
CI2CA
41
DSCL
20
DSDA
19
CVCC18
4
CVCC18
16
CVCC18
45
CVCC18
59
CVCC18
74
CGND
3
CGND
15
CGND
46
CGND
60
CGND
73
IOVCC
48
IOVCC
71
IOGND
47
IOGND
72
IC1102
SII9030
TQFP-80
DGND
C1141
100N
16V
0603
C1140
100N
16V
0603
C1139
100N
16V
0603
ADJ
REG1102
LM1086CS-ADJ
TO-263
C1143
100N
50V
0805
R1100
120R
0W125
0805
R1101
56R
0W125
0805
DGND
P1134
C1142
100UF
10V
YXF
+3V3D
+1V8_HDMI
DGND
ABCLK_HDMI
ALRCLK
ADAT0
ADAT1
ADAT2
R1102
2K2
0W063
0603
R1103
2K2
0W063
0603
P1136
P1135
BOTTOM
BOTTOMBOTTOMBOTTOM
BOTTOMBOTTOM
BOTTOMBOTTOM
Some decoupling
caps are on
bottom of PCB
DGND
R1108
470R 0603
DSA
1
DSB
2
Q0
3
Q1
4
Q2
5
Q3
6
Q4
10
Q5
11
Q6
12
Q7
13
CP
8
MR
9
IC1103A
74LV164D
S0-14
1I0
2
1Y
4
2Y
7
1I1
3
3Y
9
4Y
12
2I0
5
3I0
11
3I1
10
2I1
6
4I0
14
4I1
13
S
1
EN
15
IC1104A
74LVC157AD
S0-16
+3V3D
HSYNC*
HSYNC*
CLK27M_VID
+3V3D
PROG/INT*
PROG/INT*
DGND
HSYNCD*
HSYNC DELAY CIRCUIT
delays HSYNC* by 4 clocks in
progressive mode and 8 clocks in
interlaced mode. This is to ensure
HSYNC and VSYNC falling edges
are coincident as required by HDMI
specification
VCC
14
GND
7
IC1103B
74LV164D
S0-14
VCC
16
GND
8
IC1104B
74LVC157AD
S0-16
C1144
100N
16V
0603
C1145
100N
16V
0603
R1104
75R 0603
P1137
P1138
P1139
P1140
R1110
1K8
0603
R1111
1K8
0603
NF
NF
PG 1.004_E121 09-08-04 Production release
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