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Fig 3. GPIO control signals from the Vaddis V
Single Name I/P-
O/P
Function
PSUFSO-1 Output
Control PSU Clock
divider
ENABLE_AV Output
SCART control High
in normal operation
and low in standby
16/9 Output
Scart 16/9
anamorphic control
line
9190INT* Input
Interrupt signal
from SII9190 HDMI
transmitter
GAIN_SCALING Output
High for HDCD gain
scaling
ML_8740_0-2 Output
SPI load signal for
Audio DACs 0,1 and
2 (see note 1)
MC Output
SPI clock signal for
DAC control
MD Output
SPI data signal for
DAC control
FSELE0-1 Output
Frequency select
generator
MUTE* Output
Active low audio
mute signal
DDC_SDA,DDC,SCL I/O
12C bus for DDC
channel on HDMI
interface
PROG_INT* Output
High for Progscan
mode, Low for
interlaced mode.
Controls Sil9130
data mux
HDMI_RESET* Output
Reset signal for
HDMI transmitter
RESET* Output
System reset
Clocks and SPDIF stage.
IC300
is a
SM8707E
clock generator IC. This IC is
sensitive to noise on it’s power supply, which causes
clock jitter for this reason we have a independent Low
dropout – low noise
+3v3
power supply for the chip
based around the regulator at location
REG300
.
X300
is a
27Mhz
crystal that
IC300
uses to generate
all the video and audio clocks required by the system
the crystal sits on the XTI and XTO pins of the chip,
the 27Mhz output at Pin 4 (MO2) is used to drive the
Vaddis chip directly bypassing the internal PLL.
The frequency of the audio master is dependent on
the on the current audio sample rate (I.e the sample
rate required by the format CD=44.1Khz and
DVD=48khz etc) and this is set by the system micro
via the
FSLO
and
FSEL1
this selects either the
22.5792Mhz or 24.576Mhz clock from frequency from
IC300 this may then be divided by 2 by the clock
divide chip at location IC306 depending on the status
of FSEL1. Therefore 4 clock frequencies may be
obtained to support all required audio samples rates.
Nand gate
IC303 is used to gate FSEL1 with
ENABLE_AV (which is low in standby mode) as such
when in standby mode the audio clock is disabled.
Clock Buffer
IC301 us used to buffer the audio master clock. The circuit
is arranged so that each device that requires the audio
master clock has it’s own driver these are seen as.
o MCLK_DAC0 - Pin 18
o MCLK_DAC1 – Pin 16
o MCLK_DAC2 – Pin 14
o
MCLK_VADDIS – Pin 3
o MCLK_HDMI – Pin 9
We also run the
Mute Line
from the Vaddis V
IC301
this
can be seen on Pin 12 and drives transistor
TR401
, the
transistor pulls the relays RLY400, RLY500, RLY600 to
ground and un-mutes the audio outputs.
IS2 Audio Data
IC302
and
IC309
are buffers for the 12S signals these
ensure that the signals travelling to the DAC’s are point to
point.
IC302
deals with the
ALRCK
and
ABCLK
and
IC309 the ADAT0,1,2 all signal are split into three
separate lines for the three stereo DACS.
PSU Clock Divider
IC304
and
IC305
form a clock divide by 1, 2 or 4 to ensure
the PSU clock is always either 44.1kHz or 48Khz (
See fig
1
within the power supply description section).
This circuit will also switch the PSUCLK off when
switching between sample rates (the PSU will free run
when the PSUCLK is not present).
SPDIF Output
The SPDIF output consists of
IC308
implemented as a
inline buffer and parallel output buffer. Gate A buffers the
signal so that the SPDIF line from the VADDIS sees fewer
loads and form a feed to the Optical output transmitter,
gates B,C and D drive the SPDIF in parallel so that we can
drive a 75ohm load adequately. The resistors at the output
of IC308 are arrange so that the output will be 500mV pk-
pk
when the output is terminated with a 75 ohm load at the
same time the output impedance of the circuit is 75ohms
as required by the Sony Philips Digital Interface
specification, the transformer at location TX301 electrically
isolates the SPDIS output.