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HYUNDAI MicroElectronics GMS90X5XC Series
18 Jan. 2001 Ver 1.0
TIMER / COUNTER 0 AND 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
In the "timer" function (C/T
= "0") the register is incremented every machine cycle. Therefore the count rate is
f
OSC
/12.
In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter-
nal input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate
is f
OSC
/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate
pulse width measurements. Figure 4 illustrates the input clock logic.
Figure 4. Timer/Counter 0 and 1 Input Clock Logic
Table 4. Timer/Counter 0 and 1 Operating Modes
Mode Description
TMOD Input Clock
Gate C/T M1 M0 internal external (Max.)
0 8-bit timer/counter with a
divide-by-32 prescaler
XX00f
OSC
÷
(12
×
32) f
OSC
÷
(24
×
32)
1 16-bit timer/counter X X 0 1 f
OSC
÷
12 f
OSC
÷
24
2 8-bit timer/counter with
8-bit auto-reload
XX10 f
OSC
÷
12 f
OSC
÷
24
3 Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer Timer 1
stops
XX11 f
OSC
÷
12 f
OSC
÷
24
f
OSC
÷
12
TMOD
f
OSC
÷
12
P3.4/T0
P3.5/T1
Max.
f
OSC
/24
C/T
=1
≥
1
TCON
TR0 / 1
TMOD
Gate
&
P3.2 / INT0
P3.3 / INT1
Timer 0/1
Input Clock
0
1