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Block Diagrams, Test point Overview, and Wave Forms
EN 27FHP PDP 6.
6. Block Diagrams, Test point Overview, and Wave Forms
6.1 Block Diagrams
Figure 6-1 Signal block diagram
G_16400_021.eps
190706
PFCgo
Vsago
Vcego
CN69
CN7
PSU
DATA CONVERTER
Y-SCAN
EVEN SW
X-SCAN
EVEN SW
ABUS-R
ABUS-L
X
-
B
U
S
S
D
M
-
U
S
D
M
-
D
SCAN CONTROLLER
FRAME
MEMORY
DATA PROCESSOR
OSC
TIMING ROM
γ comp.
OSC
80MH
MPU
OSC
10MHz
Y-SUS
X-SUS
LOGIC Board
Y-SUS
EVEN SW
X-SUS
EVEN SW
CN31
Y-SUS
ODD SW
Y-SCAN
ODD SW
X-SUS
ODD SW
X-SCAN
ODD SW
RGB
GAIN
DITHER
/ERR
SUB FIELD
PRC.
POS
RESET SW
POS /NEG
RESET SW
MEMORY
CONTROLLER
ADM1 ADM4 ADM8ADM7ADM6ADM5ADM3ADM2
LVDS
24MHz
SIGNAL
INPUT
Vrs
Vra
Vrw
Vrx
D/A
V-SYNC cont
.
APC cont
.
I/O
EEPROM
Failure DET.
FLASH
Analog Sw
OSC
40MH
CN1
CN3
CN2
CN21
SCI.
I
2
C
CN5
CN41CN51
CN4