A SERVICE OF

logo

561
Chapter 31 External Bus
4.Endian and Bus Access
8-bit bus
width
Big endian mode Little endian mode
AA
AA
WR0
address: "0"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
AA
AA
WR0
address: "0"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
BB
BB
WR0
address: "1"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
BB
BB
WR0
address: "1"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
CC
CC
WR0
address: "2"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
CC
CC
WR0
address: "2"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
DD
DD
WR0
address: "3"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24
DD
DD
WR0
address: "3"
D00
D31
D31
Internal External Control
Reg terminal terminal
(1)
D24