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Circuit Descriptions and List of Abbreviations
EN 74 DVD763SA9.
9.5 Control and Display
9.5.1 Control
The key component on this board is the (slave) microprocessor
(item 7101). It runs on an 8 MHz system clock generated with
a ceramic resonator (item 1128) and has a reset circuit that is
triggered by the +5VSTBY voltage.
After the RESET pulse (active LOW), the STB_CTRL line (pin
21, item 7101) will release the reset of the host uP (on the
mono board) via the switched 3V3 supply. See circuit around
item 7409 on mono board (diagram M4).
Other slave processor functions are:
• Generation of a scanning grid for the keys.
• Generation of the display grid and segment scanning.
• Generation of a square signal to generate the filament
voltage for FTD display.
• Input for RC5/6 remote control protocol. The logic is HIGH
> 4.5V and LOW < 0.3V.
Standby LED
Transistor 7105 drives the Standby LED. When the STBY_LED
signal from the slave processor is ‘high’, the LED is ‘off’.
Key Matrix
When a key on the local keyboard is pressed, the signal at the
scanning pins of the microprocessor (pins 26 to 37) goes from
+5V to 0V.
IR Receiver
The IR controller in the slave processor handles both RC5 and
RC6 signals. The logic is +5V for ‘high’ and 0V for ‘low'
(measure at pin 22).
P50 Interface
P50 (or Easylink) is a bi-directional serial interface for
communication between video equipment. This
communication goes via pin 10 of the SCART-bus.
9.5.2 Display
The slave uP provides a negative DC switching voltage, to
drive the 11-segment FTD. As the display consists of eleven
segments, there are eleven grid signals (G1-G11) controlling
each respective grid.
The slave processor has an internal square signal generator
(42 kHz with duty cycle 45/55), to generate the AC filament
voltage. TS7103 and 7106 amplify the square signal before it is
applied to the display (VAC= VFIL_1 - VFIL_2, VRMS ≈ 3.5 V).
The necessary power supply of -26 V is derived (via zener
diode 6101) from the -32V supply, which is coming directly from
the Switching Mode Power Supply (SMPS).
Figure 9-12 Slave processor interface
The block diagram above, illustrates the interfaces of the slave
uP. The start-up sequence is as follows:
1. The required IC voltage is the +5VSTBY, which is present
during Standby Mode.
2. When the RESET circuit (item 7102) is triggered by the
+5VSTBY, the slave uP initialises.
3. This will set the STDBY_CTRL signal to LOW, which will
switch on the +3V3 and +5V.
4. Once these voltages are provided, the host uP (on the
mono board) will reset.
5. Now, the host uP will initialise, and indicate the slave uP to
activate the Standby Mode (STBY_CTRL) signal.
6. The player wakes up from the Standby Mode when any
button is pressed on the front panel, or when the 'Power'
button is pressed on the Remote Control.
Note: The slave uP will not reset successfully, if the 8MHz
clock oscillator has not stabilised (check on pin 8 of IC7101).
TMP87CH74
slave uP
FRONT CTRL
(Tact Switch)
FRONT STDBY
(1 x Tact Switch)
OPEN|CLOSE
STOP
PLAY|PAUSE
STDBY|ON
SEGMENT
GRID
IR
STDBY_CTRL
SIO_DATA
SIO_CLK
FTD
A/V BOARD
*
STDBY_CTRL LED
OTHERS
STi55xx
HOST
SIO_CLK
SIO_DATA
* For DVD763SA models
CL 26532053_060.eps
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