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4.6ClocksTab
4.6.1ConfiguringtheCodecClocksandFsrefCalculation
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TLV320AIC3007EVMSoftware
Figure9.ClocksTab
TheTLV320AIC3007providesaphase-lockedloop(PLL)thatallowsflexibilityintheclockgenerationfor
theADCandDACsamplerates.TheClockstabcontainsthecontrolsthatcanbeusedtoconfigurethe
TLV320AIC3007foroperationwithawiderangeofmasterclocks.SeetheAudioClockGeneration
ProcessingfigureintheTLV320AIC3007datasheetforfurtherdetailsofselectingthecorrectclock
settings.
ForusewiththePCsoftwareandtheUSB-MODEVM,theclocksettingsmustbesetacertainway.Ifthe
settingsarechangedfromthedefaultsettingswhichallowoperationfromtheUSB-MODEVMclock
reference,theEVMsettingscanberestoredautomaticallybyclickingtheLoadEVMUSBSettings
button.Notethatchanginganyoftheclocksettingsfromthevaluesloadedwhenthisbuttonispushed
canresultintheEVMnotworkingproperlywiththePCsoftwareorUSBinterface.Ifanexternalaudiobus
isused(audionotdrivenovertheUSBbus),thensettingscanbechangedtoanyvalidcombination.See
Figure9.
ThecodecclocksourceischosenbytheCODEC_CLKSourcecontrol.Whenthiscontrolissetto
CLKDIV_OUT,thePLLisnotused;whensettoPLLDIV_OUT,thePLLisusedtogeneratetheclocks.
Note:PertheTLV320AIC3007datasheet,thecodecmustbeconfiguredtoallowthevalueof
Fsreftofallbetweenthevaluesof39kHzto53kHz.
SLAU286–June2009TLV320AIC3007EVM-K15
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