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In summary form, the registers and their function are listed in the following table.
Each register has eight bits which can constitute a byte of data or eight individual
read/write functions. The CIO-DAC08 has 8 pairs of register (Base + 0 through
Base + 15) and the CIO-DAC16 has 16 pairs of register (Base + 0 through Base +
31).
Table 4-2. Register Map
SameAnd so on for each DACBASE + ##
...
Intiate simultaneous updateD/A 4 Least Significant ByteBASE + 8
Intiate simultaneous updateD/A 3 Most Significant NibbleBASE + 7
Intiate simultaneous updateD/A 3 Least Significant ByteBASE + 6
Intiate simultaneous updateD/A 2 Most Significant NibbleBASE + 5
Intiate simultaneous updateD/A 2 Least Significant ByteBASE + 4
Intiate simultaneous updateD/A 1 Most Significant NibbleBASE + 3
Intiate simultaneous updateD/A 1 Least Significant ByteBASE + 2
Intiate simultaneous updateD/A 0 Most Significant NibbleBASE + 1
Intiate simultaneous updateD/A 0 Least Significant ByteBASE + 0
READ FUNCTIONWRITE FUNCTIONADDRESS
The DAC16 contains 32 registers (16 register pairs). The DAC08 contains 16
registers. Each register-pair controls one D/A output.
Each DAC has two 8-bit registers which are used to control it. The first register
contains the least significant eight bits of D/A code and should be written first.
D12
(LSB)
D11D10D9D8D7D6D5
01234567
The second register contains the most significant four bits of D/A code and should
be written to second. A write to this register updates the output of the D/A with all
12 bits of the D/A code contained in the two registers. If the XFER jumper is set for
the DAC, no update will occur until a read of any one of the DAC registers is
executed. Upon a read, all DACs set for simultaneous update (XFER jumper set)
will update together.
D4D3D2D1
(MSB)
XXXX
01234567
10