54 SPARC Enterprise Mx000 Servers Administration Guide • November 2007
Domain Resource Assignment
The assignment of CPU modules (CPUM), memory, and I/O to domains in Quad-
XSB mode is shown in
TABLE 4-2, TABLE 4-3 and TABLE 4-4.
TABLE 4-2 Resource Assignment in Quad-XSB Mode on an M4000 Midrange Server
XSB CPU Memory Board I/O
00-0 CPUM#0-CHIP#0 MEMB#0 Disks; GbE; PCI#0,
PCI#1, PCI#2
00-1 CPUM#0-CHIP#1 MEMB#1 PCI#3, PCI#4
00-2 CPUM#1-CHIP#0 MEMB#2 None
00-3 CPUM#1-CHIP#1 MEMB#3 None
TABLE 4-3 Resource Assignment in Quad-XSB Mode on an M5000 Midrange Server
XSB CPU Memory Board I/O
00-0 CPUM#0-CHIP#0 MEMB#0 Disks; GbE; IOU#0-
PCI#0, IOU#0-PCI#1,
IOU#0-PCI#2
00-1 CPUM#0-CHIP#1 MEMB#1 IOU#0-PCI#3, IOU#0-
PCI#4
00-2 CPUM#1-CHIP#0 MEMB#2 None
00-3 CPUM#1-CHIP#1 MEMB#3 None
01-0 CPUM#2-CHIP#0 MEMB#4 Disks; GbE; IOU#1-
PCI#0, IOU#1-PCI#1,
IOU#1-PCI#2
01-1 CPUM#2-CHIP#1 MEMB#5 IOU#1-PCI#3, IOU#1-
PCI#4
01-2 CPUM#3-CHIP#0 MEMB#6 None
01-3 CPUM#3-CHIP#1 MEMB#7 None
