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FX Series Programmable Controlers Applied Instructions 5
5-100
5.9.5 CCD (FNC 84)
Operation:
This instruction looks at a b
y
te (8 bit) stack of data
from head address (S)for n b
y
tes and checks the
vertical bit pattern for parit
y
and sums the total
data stack. These two pieces of data are then
stored at the destination (D).
Points to note:
a) The SUM of the data stack is stored at destination D while the Parit
y
for the data stack is
stored at D
+1
.
b) Durin
g
the Parit
y
check an even result is indicated b
y
the use of a 0 (zero) while an odd
parit
y
is indicated b
y
a 1 (one).
c) This instruction can be used with the 8 bit/ 16 bit mode fla
g
M8161. The followin
g
results will
occur under these circumstances. See pa
g
e 10-20 for more details about M8161.
It should be noted that when M8161 is OFF ‘n’ represents the number of consecutive b
y
tes
checked b
y
the CCD instruction. When M8161 is ON onl
y
the lower b
y
tes of ‘n’ consecutive
words are used.
The ‘SUM’ is quite simpl
y
a summation of the total quantit
y
of data in the data stack. The Parit
y
is checked verticall
y
throu
g
h the data stack as shown b
y
the shaded areas.
Mnemonic Function
Operands
Program steps
SDn
CCD
FNC 84
(Check
Code)
Checks the
‘vertical’ parit
y
of
a data stack
KnX, KnY, KnM,
KnS
T, C, D
KnY, KnM, KnS
T, C, D
K, H
D
Note:
n = 1 to 256
CCD,
CCDP:
7 steps
X0
K 6
[ S ] [ D ]
D0CCD D100
[ n ]
D100
M8161=OFF
1
Sourse
(
S
)
Bit patterm
H
L
1
1
1
1
1
1
1
1
1
1
1
1
1
FF
FF
1
1
1 1 1 1 1 1 1FF 1
0 0 0 0 0 0 000 0
1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1
F0
0F
D101
H
L
D102
H
L
Vertical
party
D1
0 0 0 0 0 0 0 0
SUM D0 3FC
D100 L
M8161=ON
1
Sourse
(
S
)
Bit patterm
1 1 1 1 1 1FF 1
00
1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1
F0
0F
Vertical
party
D1
1 1 1 1 1 1 1 1
SUM D0 2FD
D101 L
D102 L
D103 L
D104 L
D105 L
F0
0F
1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0