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FX Series Programmable Controllers PLC Device Tables 8
8-4
8.3 Performance Specification Of The FX (CPU versions 2.0 to 3.06)
continued over the pa
g
e....
Item Specification Remarks
Operation control method C
y
clic operation b
y
stored pro
g
ram
I/O control method
Batch processin
g
method (when
END instruction is executed)
I/O refresh instruction is available
Operation processin
g
time
Basic instructions: 0.74
µ
s
Applied instructions: several 10's to 100
µ
s
Pro
g
rammin
g
lan
g
ua
g
e
Rela
y
s
y
mbolic lan
g
ua
g
e + step
ladder
Step ladder can be used to pro-
duce an SFC st
y
le pro
g
ram
Pro
g
ram capacit
y
2000 steps built in
Expandable to 8000 steps usin
g
additional memor
y
cassette
Number of instructions
Basic sequence instructions: 20
Step ladder instructions: 2
Applied instructions: 87
A Maximum 119 applied instruc-
tions are available includin
g
all
variations
I/O confi
g
uration
Max hardware I/O confi
g
uration points 256, dependent on user selection
(Max. software addressable Inputs 128, Outputs 128)
Auxiliar
y
rela
y
(M coils)
General 1024 points M0 to M1023
Latched 524 points (subset) M500 to M1023
Special 256 points From the ran
g
e M8000 to M8255
State rela
y
s
(S coils)
General 1000 points S0 to S999
Latched 500 points (subset) S500 to S999
Initial 10 points (subset) S0 to S9
Annunciator 100 points S900 to S999
Timers (T)
100 msec
Ran
g
e: 0 to 3,276.7 sec
200 points
T0 to T199
10 msec
Ran
g
e: 0 to 327.67 sec
46 points
T200 to T245
1 msec
retentive
Ran
g
e: 0 to 32.767 sec
4 points
T246 to T249
100 msec
retentive
Ran
g
e: 0 to 3,276.7 sec
6 points
T250 to T255
Counters (C)
General
16 bit
Ran
g
e: 1 to 32,767 counts
200 points
C0 to C199
T
y
pe: 16 bit up counter
Latched
16 bit
100 points (subset)
C100 to C199
T
y
pe: 16 bit up counter
General
32 bit
Ran
g
e: -2,147,483,648 to
2,147,483,647
35 points
C200 to C234
T
y
pe: 32 bit up/down counter
Latched
32 bit
15 points (subset)
C219 to C234
T
y
pe: 16 bit up/down counter