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Functional Description
54
SLES140A—March 2007TVP5147M1PFP
2.11.49 F-bit and V-bit Control 1 Register
Subaddress 69h
Default 00h
7 6 5 4 3 2 1 0
Reserved VPLL Adaptive Reserved F-bit mode [1:0]
VPLL: VPLL time constant control
0 = VPLL adapts the time constant to the input signal (default)
1 = VPLL time constants are fixed
Adaptive:
0 = Enable F-bit and V-bit adaptation to detected lines per frame (default)
1 = Disable F-bit and V-bit adaptation to detected lines per frame
F-bit mode [1:0]:
00 = Auto mode. If lines per frame is standard decoded F and V bits as per 656 standard from line count
else decode F bit from VSYNC input and set V-bit = 0 (default).
01 = Decode F and V bits from input syncs
10 = Reserved
11 = Always decode F and V bits from line count
This register is used in conjunction with the F-bit and V-bit control 2 register (subaddress 75h) as indicated
below:
Reg 69h Reg 75h
Mode
Standard LPF Nonstandard LPF
Bit 1 Bit 0 Bit 1 Bit 0
Mode
F V F V
0 0 0 0 Reserved Reserved Reserved Reserved Reserved
0 0 0 1 TVP5160 656 656 Toggle Switch9
0 0 1 0 TVP5160 656 656 Pulse 0
0 0 1 1 Reserved Reserved Reserved Reserved Reserved
0 1 0 0 Reserved Reserved Reserved Reserved Reserved
0 1 0 1 656 656 Toggle Switch9
0 1 1 0 656 656 Pulse 0
0 1 1 1 Reserved Reserved Reserved Reserved Reserved
1 0 0 0 Reserved Reserved Reserved Reserved Reserved
1 0 0 1 Reserved Reserved Reserved Reserved Reserved
1 0 1 0 Reserved Reserved Reserved Reserved Reserved
1 0 1 1 Reserved Reserved Reserved Reserved Reserved
1 1 0 0 TVP5146 656 656
Even = 1
Odd = toggle
Switch
1 1 0 1 TVP5146 656 656 Toggle Switch
1 1 1 0 TVP5146 656 656 Pulse Switch
1 1 1 1 Reserved Reserved Reserved Reserved Reserved
656 = ITU-R BT.656 standard
Toggle = Toggles from field to field
Pulse = Pulses low for 1 line prior to field transition
Switch = V bit switches high before the F bit transition and low after the F bit transition
Switch9 = V bit switches high 1 line prior to F bit transition, then low after 9 lines
Reserved = Not used