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Example Register Settings
84
SLES140A—March 2007TVP5147M1PFP
I
2
C register address 00h = Input select register
I
2
C data 46h = Sets luma to VI_2_C and chroma to VI_1_C
I
2
C register address 04h = Autoswitch mask register
I
2
C data 3Fh = Includes NTSC 443 and PAL (M, Nc, 60) in the autoswitch
I
2
C register address 08h = Luminance processing control 3 register
I
2
C data 00h = Optimizes the trap filter selection for NTSC and PAL
I
2
C register address 0Eh = Chrominance processing control 2 register
I
2
C data 04h = Optimizes the chrominance filter selection for NTSC and PAL
I
2
C register address 33h = Output formatter 1 register
I
2
C data 41h = Selects the 10-bit 4:2:2 output format
I
2
C register address 34h = Output formatter 2 register
I
2
C data 11h = Enables YCbCr output and the clock output
I
2
C register address 36h = Output formatter 4 register
I
2
C data 11h = Enables HS and VS sync outputs
4.3 Example 3
4.3.1 Assumptions
Input connector: Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)]
Video format: 480I, 576I
Output format: 20-bit ITU-R BT.656 with discrete sync outputs
4.3.2 Recommended Settings
Recommended I
2
C writes: This setup requires additional writes to output the discrete sync 20-bit 4:2:2 data,
HS, and VS, and to autoswitch between all video formats mentioned above.