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Philips Semiconductors
TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 21 of 38
9397 750 07338
© Philips Electronics N.V. 2000. All rights reserved.
9.1.5 Divider register
This register controls the PLL frequency. The bits are the LSB bits.
The default programmed value is 0011 0010 0000 = 800.
The MSB bits (Di11, Di10 and Di9) and the LSB bit (Di0) have to be programmed
before bits ‘Di8’ to ‘Di1’ are programmed, to obtain the required divider ratio. Bit ‘Di0’
is used for the parity divider number (bit ‘Di0’ = 0 means even number, while
bit ‘Di0’ = 1 means odd number). It should be noted that if the I
2
C-bus programming is
done in mode 1 (bit Mode = 1) and bit ‘Di0’ has to be toggled, then the registers have
to be loaded twice to have the update divider ratio.
9.1.6 Power-down mode
•
When the supply is completely switched off, the registers are set to their default
values; in that event they have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
•
When the device is in Power-down mode, the previously programmed register
values remain unaffected.
9.1.7 PHASEA and PHASEB registers
Bit ‘Cka’ is logic 0 when the used clock is the PLL clock, and logic 1 when the used
clock is the external clock.
Bit ‘Ckb’ is logic 0 when the second clock is not used.
Bits ‘Pa4’ to ‘Pa0’ and bits ‘Pb4’ to ‘Pb0’ are used to program the phase shift for the
clock, CKADCO, CKAO and CKBO (see Ta bl e 11 ). Concerning the PHASEB register,
bit ‘Ckab’ is used to have either CKAO or CKBO at pin CKAO (pin 81).
The default programmed value is as follows:
•
No external clock: bit ‘Cka’ is logic 0
•
No use of the second clock: bit ‘Ckb’ is logic 0
•
Phase shift for CKAO and CKADCO is 0 deg
•
Phase shift for CKBO is 0 deg
•
Clock CKAO at pin CKAO: bit ‘Ckab’ is logic 0.
Table 11: Phase registers bits
Pa4 and Pb4 Pa3 and Pb3 Pa2 and Pb2 Pa1 and Pb1 Pa0 and Pb0 Phase shift (deg)
000000
0000111.25
... ... ... ... ... ...
11110337.5
11111348.75