![](http://pdfasset.owneriq.net/6/b9/6b987e72-a4f4-4ccb-87ec-e3052083ac5a/6b987e72-a4f4-4ccb-87ec-e3052083ac5a-bgdf.png)
S3F80P5_UM_ REV1.00 RESET
STOP ERROR DETECTION & RECOVERY
When RESET Control Bit (smart option bit [0] @ 03FH) is set to ‘0’ and chip is in stop or abnormal state, the
falling edge input of P0 generates the reset signal.
Refer to following table and figure for more information.
Table 8-1. Reset Condition in STOP Mode
Condition
Slope of V
DD
V
DD
Reset
Source
System Reset
Rising up from V
POR
< V
DD
< V
LVD
V
DD
≥ V
LVD
– No system reset
Rising up from V
DD
< V
POR
V
DD
≥ V
LVD
Internal POR System reset occurs
8-7