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CONTROL REGISTERS S3F80P5_UM_ REV1.00
RESETID — Reset Source Indicating Register F0H Set1 Bank1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
Read/Write
− − −
R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7− .4
Not used for S3F80P5.
.3 Key-in Reset Indicating Bit
0 Reset is not generated by P0, P2 external INT
1 Reset is generated by P0, P2 external INT
.2 WDT Reset Indicating Bit
0 Reset is not generated by WDT (when read)
1 Reset is generated by WDT (when read)
.1 LVD Reset Indicating Bit
0 Reset is not generated by LVD (when read)
1 Reset is generated by LVD (when read)
.0 POR Reset Indicating Bit
0 Reset is not generated by POR (when read)
1 Reset is generated by POR (when read)
State of RESETID depends on reset source
.7 .6 .5 .4 .3 .2 .1 .0
POR
− − −
0 0 0 1 1
LVD
− − −
0 0 0 1
(note2)
WDT, Key-in
− − − −
(note3) (note2)
NOTES:
1. To clear an indicating register, write a “0” to indicating flag bit. Writing a “1” to a reset indicating flag (RESETID.0-.3) has
no effect.
2. Not affected by any other reset.
3. Bits corresponding to sources that are active at the time of reset will be set.
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