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* The flicker is caused by one SDRAM
bank displaying bad data and the other
bank displaying good data. This results in
bad data displayed every other frame.
The freeze command stops the SDRAM
buffers(A&B) from toggling between read
& write. This is useful in seeing the output
from one SDRAM bank at a time
Bad image-1 to 32
pixel wide columns
that repeat every 32
pixels and flickers
at half the frame rate
Bad image-16
pixel wide vertical
column(s)
Bad image-all or
most of image is
corrupted and
flickers at half the
frame rate
Bad image-
Corrupted color
ramp test image
Bad image-
Horizontal bands
or lines
2
1. Check DMD elastomer interconnect
2. Check outputs from DMDSR16C(U88)
3. Check input voltages to DMDSR16C
4. Replace DMD or DMDSR16C if needed
5. Check VCC2 Voltage is 7.5V
1. Check DMD elastomer interconnect
2. Check DMD data outputs from DPF2A ASIC(U77)
1. Check interconnect on data inputs GY(8:0),
RV(7:0),BU(7:0)
2. Check color wheel alignment
3. Check CWINDEX has only one rising edge
transition per color wheel revolution
4. Check color wheel is running in correct
direction
5. Verify sequence version is correct from
color wheel
6. Verify flash checksum
7. Verify the color wheel is runing at correct
rate(92-128Hz)
1. Check data interconnect between SDRAMs
and DPF2A ASIC
2. Replace SDRAM(U78~U81) or DPF2A if needed
N
N
N
Y
Y
Y
N
Y
Y
N
1
1. Check address and control signal
interconnects between FPGA(U76) and the
SDRAMs
2. Replace FPGA or SDRAMS if needed