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48DVD963SA 7.
Electrical Diagrams
AV-Board: Upsampling
FSIN
FIR
FIL
ROM
SERIAL OUTPUT
DIG
PLL
FS
OUT
DGND
SERIAL INPUT
CLOCK
DIV
FIFO
EN
G1
1
MUX1~
2
1
3EN2
3EN1
G3
PARALLEL LOAD
BINARY COUNTER
PARALLEL LOAD
BINARY COUNTER
+3V3D
3208 H12
3210 I9
3211 I9
3212 F7
2211 I12
2212 I10
2213 B4
3200 E5
3201 E4
3202 E5
3203 H2
74AC00M
12
I203 D4
I207 G3
I208 H3
6789345
7206-D E11
7206-E A10
7206-F F13
7207-A C12
7207-B E12
7207-C C13
12 13
A
H
I
A
I218 F5
I219 F7
I220 D13
I222 E13
I223 H12
I224 H12
I225 I12
74AC00M
F
G
I209 H2
I212 D12
I214 E6
I215 E4
I216 E5
I217 F4
B
3213 H3
3214 I12
B
C
D
E
74AC00M
74AC00M
3204 F3
3205 H13
3206 H9
3207 H13
7206-A B6
7206-B A7
7206-C A8
E
F
G
H
I
2200 B6
2201 B13
2202 C4
2203 C11
2204 C8
3V
1V6
1V6
1V6
1V6
0V
0V
10 11
7207-D B12
7220 H2
7221 E7
7222 I3
I200 C4
I201 C4
I202 D4
67891011
V DC Vtg measured in STOP-MODE
* RESERVED
UPSAMPLING
12 13
12345
3V3
A3
A3
A3
A3
A1
A1
C
D
3215 I2
7200 B4
7201 F4
7202 F7
7203 G10
7204 C7
7205 C10
2205 F4
2206 F5
2207 F4
2208 F5
2209 F8
2210 G3
1V61V6
A1
0V
1V6
1V6
5V
3V
1V4
0V
A1
A1
A1
A1
A1
A1
A1
0V7
1V6
5V
3V3
1V6
5V
A1
A1
A1
A1
A1
A1
A1
0V
5V
17WLNGTH-O-0
16WLNGTH-O-1
BARE BOARD : 3139-243-30533
0V
0V
1V6
0V7
1V6
1V6
1V6
1V6
0V
0V3
1V6
1V6
A6
A6
1V6 1V6
1V6
1V6
0V
1V8
3V3
2V4
1V8
5V
1V
0V
3V3
MUTE-O 15
1
NC
13 RESET_
5 SCLK-I
SCLK-O 25
4 SDATA-I
23SDATA-O
10 SMODE-IN-0
11 SMODE-IN-1
12 SMODE-IN-2
19SMODE-O-0
18SMODE-O-1
20TDM-I
22
VDD-CORE
7
VDD-IO
AD1895
7201
9 BYPASS
821
LRCLK-I6
24LRCLK-O
2 MCLK-I
3
MCLK-O
26 MMODE-0
27 MMODE-1
28 MMODE-2
14 MUTE-I
+5VD
+3V3D
2208
100n
100n
2209
27K
3203
+5VD
2206
10u
+5VD
3208
330R
3205
2K2
2K2
3207
2K2
3214
I217
I218
1
2
7
14
3
100n
2207
7207-A
+5VD
+5VD
4
5
7
14
6
2200
100n
7207-B
3204
4K7
BC847B
7221
10u
2205
74LVC04
7206-A
1
7
14
2
3212
4K7
7207-D
12
13
7
14
11
+5VD
I212
74LVC04
7206-B
3
7
14
4
+3V3D
I220
I223
7
14
12
1R
3201
+5VD
2211
100n
74LVC04
7206-F
13
100n
2202
+3V3D +3V3D
2K2
3210
9
14
13
12
15
GND
8
1
VCC
16
7200
74LVC157A
2
3
4
5
6
7
11
10
+3V3D
+5VD
MR_1
PE_9
Q0 14
Q1 13
Q2 12
Q3 11
TC 15
16
VCC
7204
74LVC161
CEP
7
CET10
CP2
D03
D14
D25
D36
8
GND
FS1|CDTI
9
FS2|CCLK
10
FS3|CDTO
11
LRCK
7
MCLK
4
PDN
3
SDTI
5
TRANS
2
TXN
19
TXP
20
U1
24
V1
1
VDD
17
VSS
18
7203
AK4103VF
ANS
13
BICK
6
BLS
14
C1
12
CKS0
15
CKS1
16
DIF0
21
DIF1
22
DIF2
23
FS0|CSN
8
+3V3D
+3V3D
27K
3215
BC847B
7222
2K2
3213
I208
I207
14
8
3202
1R
10
GND
19
1
20
VCC
7207-C
9
10
7
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
+5VD
+3V3D
74LVC245
7202
2
+3V3D
2204
100n
+5VD
I224
I214
I225
3200
27K
100n
2201
+5VD
5
7
14
6
7220
BC847B
2K2
3206
74LVC04
7206-C
3211
2K2
74LVC04
7206-E
11
7
14
10
100n
2203
35V 10u
2213
+3V3D
I219
I216
10u
2212
74LVC04
7206-D
9
7
14
8
I215
10u
2210
TC 15
16
VCC
+5VD
CEP
7
CET10
CP2
D03
D14
D25
D36
8
GND
MR_1
PE_9
Q0 14
Q1 13
Q2 12
Q3 11
I209
74LVC161
7205
+5VD
+5VD
+5VD
LRCLK
Upsampling
192K_96K
24.576M
Upsampling
24.576M
192K_96K
SPDIF_MUTE
SDT1
FR_DATA
BCLK
FR_BCK
LRCLK
FR_LRCK
24.576M
MCLK1
FR_MCLK
Upsampling
DIG_OUT
SPDIF_OUT
SDT1
BCLK
AD1895_CLK
CL 26532105_006.eps
020902
2V / div DC
50ns / div
12.288M
2V / div DC
2us / div
192k
2V / div DC
2us / div
I200
2V / div DC
100ns / div
I202
2V / div DC
10us / div
I201
2V / div DC
20ns / div
I203
500mV / div DC
200ns / div
I222
I200
I201
I203
I202
I222
192k
12.88M