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18
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
STATUS/
COMMAND
REGISTER
RESET
LOGIC
RECONFIGURATION
TIMER
NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
ADDRESS
DECODING
CIRCUITRY
2K x 8
AD0-AD2,
BUS
ARBITRATION
CIRCUITRY
nPULSE1
nPULSE2
nTXEN
XTAL1
XTAL2
nINTR
nRESET IN
RAM
A
0
/
n
M
U
X
A
1
A
2
/
B
A
L
E
nRD/nDS
nWR/DIR
nCS
D3-D7
RXIN
FIGURE 6 - INTERNAL BLOCK DIAGRAM