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53
A0-A2
VALID DATA
VALID
D0-D7
Parameter
min max units
nCS
t8
t1
t9
t3
t6
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
*
T is twice XTAL1 period if SLOW ARB = 1
t4
t2
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2
t6**
Note 1:
Note 2:
Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4T from the trailing edge of nDS to the leading
edge of the next nDS.
t5
DIR
t7
nDS
**nCS may become active after control becomes active, but the data setup time will
now be 30 nS measured from the later of nCS falling or Valid Data available.
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)**
DIR Hold from nDS Inactive
Valid Data Setup to nDS High
Data Hold from nDS High
t1
t2
t3
t4
t5
t6
t7
t8
t9
15
10
5
0
10
4T*
10
30**
10
nS
nS
nS
nS
nS
nS
nS
nS
nS
FIGURE 13A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE