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TIMING DIAGRAMS
AD0-AD2,
VALID
nCS
t1
t3
t8
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
*
T is twice XTAL1 period if SLOW ARB = 1
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
DIR
t9
t10
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
nDS High to Data High Impedance
Cycle Time (nDS Low to Next Time Low)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
30
10
10
20
15
0
4T*
10
10
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Note 1:
nDS
FIGURE 10 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE