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A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
T is the Arbitration Clock Period.
T is identical to XTAL1 if SLOW ARB = 0,
*
T is twice XTAL1 period if SLOW ARB = 1
t4
t2
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Parameter
min
max units
t1
t2
t3
t4
t5
t6
t7
15
10
5**
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to DS Active
nCS Hold from DS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Active
4T*
nS
nS
nS
nS
nS
nS
nCS may become active after control becomes active, but the access time will
now be 45nS measured from the leading edge of nCS.
Note 1:
**
nDS
DIR
t5
t7
t8 nSnDS Low to Valid Data 40
t9 nSnDS High to Data High Impedence
20
10
10
0
FIGURE 12A - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE