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dCS 904 User Manual Manual for Software Version 1.5x and 1.36
dCS Ltd June 2000
Manual part no: DOC135904 iss 2B2
Page 58
135904ma2b2.pdf file available from website
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Check Master Clock has changed frequency. If it has not go back to step
5.
Transmit -> [1][REQUEST_FS], request actual frequency
Responds -> [ACK immediate][1], actual frequency
The system is now set up with the Master Clock configured for 96k operation
and the ADCs and DACs locked in PCM mode to 96k.
Example: Switching to P3D -
Change the Master Clock frequency to 44.1k prior to changing the ADC and
DAC operating mode to DSD. Change the DAC operating mode prior to the
ADC. When changing the Master Clock frequency the system should be
allowed to settle to the new frequency before any further RS-232 activity.
6) Command Master Clock to change frequency. Allow the system time to
settle after this command with no RS-232 activity, three seconds should
be sufficient.
Transmit -> [1][SEL_FS], change to 44.1k
Responds -> [ACK 3 seconds][1], requested frequency
Wait for 3 seconds
7) Check Master Clock has changed frequency. If it has not go back to step
6.
Transmit -> [1][REQUEST_FS], request actual frequency
Responds -> [ACK immediate][1], actual frequency
8) Command DACs 6, 7, 8 and 9 to change mode, the units may take up to
15 seconds to complete this command (if the previous mode had been
PCM the FPGAs need to be re-loaded, which takes time). There is also
no need to wait prior to moving on to step 9.
Transmit -> [6][DSD_MODE], to change mode to P3D of unit 6
Responds -> [ACK 15 seconds][6], requested mode
Transmit -> [7][DSD_MODE], to change mode to P3D of unit 7
Responds -> [ACK 15 seconds][7], requested mode
Transmit -> [8][DSD_MODE], to change mode to P3D of unit 8
Responds -> [ACK 15 seconds][8], requested mode
Transmit -> [9][DSD_MODE], to change mode to P3D of unit 9
Responds -> [ACK 15 seconds][9], requested mode
9) Command ADCs 2, 3, 4 and 5 to change mode, the units may take up to
15 seconds to complete this command (if the previous mode had been
DSD the FPGAs need to be re-loaded, which takes time). There is also
no need to wait prior to moving on to step 10.
Transmit -> [2][DSD_MODE], to change mode to P3D of unit 2
Responds -> [ACK 15 seconds][2], requested mode
Transmit -> [3][DSD_MODE], to change mode to P3D of unit 3
Responds -> [ACK 15 seconds][3], requested mode
Transmit -> [4][DSD_MODE], to change mode to P3D of unit 4
Responds -> [ACK 15 seconds][4], requested mode
Transmit -> [5][DSD_MODE], to change mode to P3D of unit 5
Responds -> [ACK 15 seconds][5], requested mode