AMD Confidential
User Manual November 21
st
, 2008
116 Chapter 7: Device Configuration
<Event Device="CPU0" Type="MEMW" ICount="3133971259"
Address="00000000000A88B2" Size="1">
<Data Length="1" Value="01" />
</Event>
Defines a Memory Read or Memory Write event. MEMR and MEMW are recorded for
MMIO ranges.
7.22.2.2 XTR Binary File Contents
XTR Binary file contains the memory image of the system just before the XTR Record
started. The binary file contains multiple records where each record contains has the
following structure:
Physical Address Of the Page: 8 bytes
Count of Bytes in this Page: 4 Bytes
Data Of the Page: Count of Bytes earlier
Currently XTR only supports page size of 4096 bytes. Both the DIMM and MMIO may
be present in the XTR Binary file. The last record in the binary file must have a count of
zero to indicate end of memory image.
7.22.3 ModeFlags
ModeFlags defines some of the states of the CPU that are important for execution. The
upper 32 bits store the Execution Control flags e.g. HLT and <ignore interrupts for 1
instruction when we change stack segment>. The lower 32 bits is redundant from other
initialization values in the XTR initialization but is there to maintain code consistency.
Table 7-7 shows the Execution Control Flags (upper 32 bit):
Pseudo pin that stops simulation
Table 7-7: Execution Control Flags
Table 7-8 shows other internal execution control flags. Some flags may be AweSim
specific.
SMC detected in current translation (restart required).
SVM virtual interrupt pending
