AMD Confidential
User Manual November 21
st
, 2008
222 Appendix A
Store global descriptor table register to
memory.
Store global descriptor table register to
memory.
Store interrupt descriptor table register to
memory.
Store interrupt descriptor table register to
memory.
Store the segment selector from the local
descriptor table register to a 16-bit
register.
Store the segment selector from the local
descriptor table register to a 32-bit
register.
Store the segment selector from the local
descriptor table register to a 64-bit
register.
Store the segment selector from the local
descriptor table register to a 16-bit memory
location.
Store the low 16 bits of CR0 to a 16-bit
register.
Store the low 32 bits of CR0 to a 32-bit
register.
Store the entire 64 bits of CR0 to a 64-bit
register.
Store the low 16 bits of CR0 to memory.
Set interrupt flag (IF) to 1.
Store the segment selector from the task
register to a 16-bit general-purpose
register.
Store the segment selector from the task
register to a 32-bit general-purpose
register.
Store the segment selector from the task
register to a 64-bit general-purpose
register.
Store the segment selector from the task
register to a 16-bit memory location.
Exchange GS base with KernelGSBase MSR.
Return from operating system.
Return from operating system.
Raise an invalid opcode exception.
Set the zero flag (ZF) to 1 if the segment
selected can be read.
Set the zero flag (ZF) to 1 if the segment
selected can be written.
Write modified cache lines to main memory,
invalidate internal caches, and trigger
external cache flushes.
Write EDX:EAX to the MSR specified by ECX.
Table 15-9: System Instruction Reference
A.6.3.1 INT – Interrupt to Vector
Interrupt to Debug Vector.
