AMD Confidential
User Manual November 21
st
, 2008
Appendix A 225
A.6.7 Extension to the 3DNow! Instruction Set
This section describes the five new DSP instructions added to the 3DNow! Instruction
set.
Packed floating-point to integer
word conversion with sign extend.
Packed floating-point negative
accumulate.
PFPNACC mmreg1,mmreg2/m64
Packed floating-point mixed
positive-negative accumulate.
Packed 16-bit integer to floating-
point conversion.
Table 15-11: Extension to 3DNow! Instruction Reference
A.6.8 Prescott New Instructions
Prescott New Instruction technology for the x64 architecture is a set of 13 new
instructions that accelerate performance of Streaming SIMD Extension technology,
Streaming SIMD Extension 2 technology, and x87-FP math capabilities. The new
technology is compatible with existing software and should run correctly, without
modification. The thirteen new instructions are summarized in the following section. For
detailed information on each instruction refer to a complete Instruction Set Reference.
Add/Subtract packed double-precision
floating-point number from XMM2/Mem
to XMM1.
Add/Subtract packed single-precision
floating-point number from XMM2/Mem
to XMM1.
Store ST as a signed integer
(truncate) in m16int and pop ST.
Store ST as a signed integer
(truncate) in m32int and pop ST.
Store ST as a signed integer
(truncate) in m16int and pop ST.
Add horizontally packed double-
precision floating-point numbers
from XMM2/Mem to XMM1.
Add horizontally packed single-
precision floating-point numbers
from XMM2/Mem to XMM1.
Subtract horizontally packed double-
precision floating-point numbers
from XMM2/Mem to XMM1.
Subtract horizontally packed single-
precision floating-point numbers
from XMM2/Mem to XMM1.
Load 128 bits from Memory to XMM
register.
