AMD Confidential
User Manual November 21
st
, 2008
226 Appendix A
Sets up a linear address range to be
monitored by hardware and activates
the monitor. The address range
should be of a write-back memory
caching type.
Move 64 bits representing the lower
double-precision data element from
XMM2/Mem to XMM1 register and
duplicate.
Move 128 bits representing packed
single-precision data elements from
XMM2/Mem to XMM1 register and
duplicate high.
Move 128 bits representing packed
single-precision data elements from
XMM2/Mem to XMM1 register and
duplicate low.
A hint that allows the processor to
stop instruction execution and enter
an implementation–dependent
optimized state until occurrence of
a class events.
Table 15-12: Prescott New Instruction Reference
A.6.8.1 MONITOR – Setup Monitor Address
The simulator does not recognize this instruction. Therefore the simulator generates an
invalid-opcode exception.
A.6.8.2 MWAIT – Monitor Wait
The simulator does not recognize this instruction. Therefore the simulator generates an
invalid-opcode exception.
1
See Section A.6.8.1, “MONITOR – Setup Monitor Address”, on page 228.
2
See Section A.6.8.2, “MWAIT – Monitor Wait”, on page 229.
