AMD Confidential
User Manual November 21
st
, 2008
206 Appendix A
Output the word in the AX register to
the port specified by an 8-bit
immediate value.
Output the doubleword in the EAX
register to the port specified by an
8-bit immediate value.
Output the byte in the AL register to
the output port specified in DX.
Output the word in the AX register to
the output port specified in DX.
Output the doubleword in the EAX
register to the output port specified
in DX.
Output the byte in DS:rSI to the port
specified in DX, and then increment
or decrement rSI.
Output the word in DS:rSI to the port
specified in DX, and then increment
or decrement rSI.
Output the doubleword in DS:rSI to
the port specified in DX, and then
increment or decrement rSI.
Output the byte in DS:rSI to the port
specified in DX, and then increment
or decrement rSI.
Output the word in DS:rSI to the port
specified in DX, and then increment
or decrement rSI.
Output the doubleword in DS:rSI to
the port specified in DX, and then
increment or decrement rSI.
Pop the top of the stack into a 16-
bit register or memory location.
Pop the top of the stack into a 32-
bit register or memory location.
Pop the top of the stack into a 64-
bit register or memory location.
Pop the top of the stack into a 16-
bit register.
Pop the top of the stack into a 32-
bit register.
Pop the top of the stack into a 64-
bit register.
Pop the top of the stack into the DS
register.
Pop the top of the stack into the ES
register.
Pop the top of the stack into the SS
register.
Pop the top of the stack into the FS
register.
Pop the top of the stack into the GS
register.
Pop the DI, SI, BP, SP, BX, DX, CX,
and AX registers.
Pop the EDI, ESI, EBP, ESP, EBX, EDX,
ECX, and EAX registers.
Pop a word from the stack into the
FLAGS register.
Pop a doubleword from the stack into
the EFLAGS register.
Pop a quadword from the stack into
the RFLAGS register.
Prefetch processor cache line into L1
data cache.
Prefetch processor cache line into L1
data cache and mark it modified.
