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12-27
Module I/O Specifications
A15 Reference
Hop Control
Outputs
To A33 Hop Controller
J2(5,8,9)
Levels: TTL
Clock Rate: ≅ 180 kHz (bursts)
Amplitude +5 Vdc
To Rear Panel
EX_10M_REF_OUT J1(13)
Waveshape: Sine
Harmonics: <-25 dBc
Signal Level: >+7.5 dBm
Spurious at >5 kHz offsets: <-110 dBc
Nominal Output Impedance: 50 Ω
To A26 Step Loop A
1M_REF_A P3(4)
Frequency: 1 MHz ± 5 Hz See
Figure 4-6 on
page 12-28
Levels: CMOS
Duty Cycle: 800 ns high, 200 ns low
Amplitude +4 Vdc
Waveshape square wave (not a true square wave)
Duty Cycle 80%
To A17 Step Loop B
1M_REF_B P3(1)
Frequency: 1 MHz ± 5 Hz See
Figure 4-6 on
page 12-28
Levels: CMOS
Duty Cycle: 800 ns high, 200 ns low
Amplitude +4 Vdc
Waveshape square wave (not a true square wave)
Duty Cycle 80%