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Intel® ICH5 AC ’97 Controller Theory of Operation
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24 AC ’97 Programmer’s Reference Manual
// Advance tail to next value
tail++;
}
3.2.4 Stopping Transfers
There are two ways that DMA transfers can be stopped.
1. By simply turning off the Bus Master run/pause bit. This will halt the current DMA transfer
immediately. Data in the output FIFOs will continue to be read out until they empty. The
registers will retain their current values and AC-link corresponding slots will be invalidated.
Setting the run/pause bit will resume DMA activity.
2. Software can stop creating new buffers and hence not update the last valid index register. The
bus master will stop once the last valid buffer has been processed. All register information is
maintained. During this condition the controller will transmit the last valid sample or zeros
pending the status of the Buffer Underrun Policy (BUP) bit in the buffer descriptor entry. If
the run/pause bit remains set, then any future update to the Last Valid Index register will cause
the bus master operation to resume.
Note: Software must ensure that the DMA controller halted bit is set before attempting to reset
registers.
3.2.5 FIFO Error Conditions
Two general conditions could result in the FIFO error bit 4 in the status register being set. Pending
the status of bit 3 in the control register it will also cause an interrupt.
3.2.5.1 FIFO Underrun
FIFO underrun will occur when the ICH5 AC ’97 controller FIFO is drained:
1. As a result of system congestion. The DMA read transaction could still be pending as data has
not returned from memory. In this case the controller will repeat last sample until new data is
available in the FIFO.
2. As a result of DMA engine reaching the Last Valid Index, no further access to memory,
therefore FIFO will drain. In this case the controller will transmit the last valid sample or
zeros pending the status of the Buffer Underrun Policy (BUP) bit in the buffer descriptor
entry. This condition is an error if software is not able to update the descriptor list before the
DMA engine reaches the Last Valid Index. However, this condition could be as result of the
completing processing the last buffer. It is up to the software driver to determine the final
status of this condition. See also Stopping Transfers, Section 3.2.4.
3.2.5.2 FIFO Overrun
FIFO overrun will occur when valid data is transmitted in proper AC-link slots and DMA FIFO
remains full. Two conditions could result in the FIFO error bit 4 in the status register being set.
Pending the status of bit 3 in the control register it will also cause an interrupt.
1. As a result of DMA engine not being able to update system memory with the content of the
FIFO. This is a result of system congestion. In this case, all new samples received from the
AC-link will be lost.