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AC ’97 Programmer’s Reference Manual 3
Contents
1
Introduction..........................................................................................................................7
1.1 About This Document.............................................................................................7
1.2 Reference Documents and Information Sources ...................................................9
2 Overview ...........................................................................................................................11
2.1 Intel
®
ICH5 AC ’97 Controller Compatibility..........................................................11
2.1.1 Third AC ’97 Component Specification Revision 2.1, Revision 2.2 and
Revision 2.3 Compliant Codecs............................................................14
2.1.2 Dedicated S/P DIF DMA Output Channel .............................................15
2.1.3 20 Bits Surround PCM Output............................................................... 15
2.1.4 Memory Map Status and Control Registers.......................................... 15
2.1.5 Second Independent Input DMA Engines.............................................16
2.1.6 PCI Local Bus Specification, Revision 2.3 Power Management...........16
2.2 General Requirements .........................................................................................16
3 Intel
®
ICH5 AC ’97 Controller Theory of Operation ...........................................................17
3.1 Intel
®
ICH5 AC ’97 Initialization.............................................................................17
3.1.1 System Reset........................................................................................17
3.1.2 Codec Topology....................................................................................17
3.1.3 BIOS PCI Configuration ........................................................................18
3.1.4 Hardware Interrupt Routing................................................................... 19
3.1.5 PCI Lock ...............................................................................................19
3.2 DMA Engines........................................................................................................20
3.2.1 Buffer Descriptor List ............................................................................20
3.2.2 DMA Initialization...................................................................................21
3.2.3 DMA Steady State Operation................................................................23
3.2.4 Stopping Transfers................................................................................ 24
3.2.5 FIFO Error Conditions...........................................................................24
3.2.5.1 FIFO Underrun ....................................................................24
3.2.5.2 FIFO Overrun ......................................................................24
3.3 Channel Arbitration...............................................................................................25
3.4 Data Buffers..........................................................................................................25
3.4.1 Memory Organization of Data ...............................................................25
3.4.2 PCM Buffer Restrictions........................................................................ 25
3.4.3 FIFO Organization.................................................................................26
3.5 Multiple Codec/Driver Support..............................................................................27
3.5.1 Codec Register Shadowing................................................................... 28
3.5.2 Codec Access Synchronization.............................................................29
3.5.3 Data Request Synchronization in Audio Split Configurations................29
3.6 Power Management .............................................................................................30
3.6.1 Codec Topologies .................................................................................30
3.6.1.1 Tertiary Codec Topologies...................................................31
3.6.2 Power Management Transition Maps ...................................................31
3.6.3 Power Management Topology Considerations..................................... 34