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Intel® ICH5 AC ’97 Controller Theory of Operation
R
AC ’97 Programmer’s Reference Manual 27
Figure 7. Incompatible Implementation of Sample Rate Conversion with Repeating Slots over
Next Frames
Frame n
Frame n + 1
Frame n + 2
Frame n + 3
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MDM
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RSVD RSVD RSVD RSVD RSVD RSVD
I/O
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TAG X
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MIC RSVD RSVD RSVD RSVD RSVD
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RSVD RSVD RSVD RSVD RSVD RSVD
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4
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5 6 7 8 9 10 11 12210 3
SYNC
Slot #
Table 11. FIFO Summary
Channel # of Samples FIFO Depth FIFO Width Comments
Mic In 1 2 32 bits 2 frame
1
dword
Mic2 In 1 2 32 bits 2 frame
1
dword
PCM In 2 4 32 bits 1 frames per dword
PCM2 In 2 4 32 bits 1 frames per dword
PCM Out 6, 4 or 2 24 32 bits 1 frames per dword (2 –16 bits ch),
1 frame per 2 dword (2 –20 bits ch)
1 frame per 2 dword (4 –16 bits ch)
1 frames per 4 dword (4 –20 bits ch)
1 frames per 3 dword (6 – 16 bits ch.)
1 frames per 6 dword (2 –20 bits ch)
Modem In 1 2 32 bits 2 frames per dword
Modem Out 1 2 32 bits 2 frames per dword
NOTES:
1. One audio frame worth of data for the specific DMA channel.
3.5 Multiple Codec/Driver Support
The ICH5 AC ’97 controller is capable of supporting a three-codec implementation. Under this
implementation all codecs share the SDATA_OUT signal while independent SDATA_IN[0:2] are
used by the codec to supply data to the controller. ICH5 allows for a compatible behavior, where
the three SDATA_IN are used, these signals are logically OR’d inside the digital controller,
effectively creating one digital input data stream. However, ICH5 also allows for an independent
SDATA_IN functionality. In this case, the SDATA_IN Map Register (SDM) MBBAR + 80h is
used to steer the content of the input slots to the appropriate controller DMA engine. This
capability also allows for a more reliable enumeration algorithm of the available codecs.