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Intel® ICH5 AC ’97 Controller Theory of Operation
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AC ’97 Programmer’s Reference Manual 37
3.6.5.4 Audio Primary Requested to D0
The audio power management procedure will attempt to get the audio codec to D0 state.
AD3 = false // set to "audio awake"
// Setting the flag first avoid race condition during D3->D0
// transition
If Audio_ready == True
{
Audio_Power_Manage_Reg = D0;
// Bring back to fully awake,
}
If MD3 == true; // (modem sleeping?)
{
Link_reset(); // cause a warm or cold reset
While (!Audio_ready); // wait for modem ready
{
read audio codec ready bit every 100ms;
}
Audio_Power_Manage_Reg = D0; // Bring back to awake,
}
3.6.5.5 Using a Cold or Warm Reset
In the pseudo code above there are several references to resetting the AC-link using
“Link_reset()”. Drivers need to differentiate if the system enters a suspend event where core power
is removed from the system before deciding to execute a Cold or Warm reset. A device is in a “D3
hot” state after the device is set in the lowest power consumption mode and core power is
maintained. A device is in a “D3 cold” state when the device is set in the lowest power
consumption mode and core power is removed.
In the ICH5 AC ’97 implementation when core power is removed the cold reset bit is reset “0”
This bit is located at:
MBBAR + 2Ch and MBAR + 3Ch
bit 1 ICH5 AC ’97 Cold Reset#.
A driver requested to resume to a D0 state from a D3 state must check the status of the ICH5 AC
’97 cold reset bit. If this bit has a value of “0” the driver will set it to “1” to de-assert the
AC_RESET# signal in the link, thus completing a cold reset. If the Cold Reset bit is set to “1” then
a warm rest is required if the AC-link is down by the procedures indicated under aggressive power
management. To execute an ICH5 AC ’97 warm reset the driver must set to “1” the ICH5 AC ’97
warm reset bit located at:
MBBAR + 2Ch and MBAR + 3Ch
bit 2 ICH5 AC ’97 Warm Reset#