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Intel® ICH5 AC ’97 Controller Theory of Operation
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AC ’97 Programmer’s Reference Manual 29
Shadowing in memory is effective as long as the codec itself does not change the value of the
registers. Therefore, the status of the GPIOs configured as inputs on the most recent frame is
accessible to software by reading the register at offset 54h in the modem codec I/O space. Only the
16 MSBs are used to return GPI status. Reads from 54h will not be transmitted across the link.
Instead, data received in slot 12 is stored internally in the controller, and the data from the most
recent slot 12 is returned on reads from offset 54h.
The Powerdown in codec offset 26h and 3Eh status registers are not supported by an automatic
shadowing mechanism, as is the case for offset 54h. However, these registers are sparingly used.
These registers are read only during power down status determination.
Finally, codec ready status is required during system initialization. It is automatically reflected in
the Global Status Register at MBBAR + 30h (MBAR + 40h) bit 8 for the SDATA_IN0 codec, bit
9 for the SDATA_IN1 codec and bit 28 for theSDATA_IN2 codec. These three bits need not be
saved in memory.
3.5.2 Codec Access Synchronization
All codec register writes are posted transactions in the ICH5 AC ’97 controller. The ICH5 AC ’97
controller will indicate transaction completion to the host processor immediately following the
request even when the transaction is actually pending for completion in the AC-link. This is done
to improve system performance. However, it also imposes restrictions in the driver(s) operation.
Also, register reads present synchronization issues.
Before a codec register access is initiated, the driver must check the status of the Codec access in
Progress (CAIP) bit 0 in the Codec Access Register at MBBAR + 34h (MBAR + 44h.) If no write
is in progress, this bit will be ‘0’ and the act of reading the register sets this bit to ‘1’. This reserves
the driver the right to perform the I/O read or write access. Once the write is complete, hardware
automatically clears the bit. The driver must also clear this bit if it decides not to perform a codec
I/O write after having read this bit. If the bit is already set, it indicates that another driver is
performing a codec I/O writes across the link and the driver should try again later.
3.5.3 Data Request Synchronization in Audio Split
Configurations
To support more than 2 channels of audio output, the AC ’97 Component Specification, Revision
2.1 allows for a configuration where up to three audio codecs work concurrently to provide
surround capabilities (refer to AC ’97 Component Specification, Revision 2.3) To maintain data on
demand capabilities the Intel controller, when configured for 4 or 6 audio channels, will wait for
all the appropriate Slot Request bits to be set before sending data in the SDATA_OUT slots. This
allows for a simple FIFO synchronization of the attached codecs.
If the codecs on the link are not compatible, or are not known to be compatible, with respect to
sample rate conversion algorithms and FIFO depth requirements (for instance, all codecs being the
same revision of the same model from the same vendor), Variable Rate support should not be
used, and a fixed sample rate of 48 MHz is recommended to maintain synchronization across the
codecs in use.