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EN 108Q549.2E LA 10.
Circuit Diagrams and PWB Layouts
2009-May-08
SSB: PNX5100 - Control
TDI
TDO
RESET_SYS
SDA
SCL
SDA
SCL
RX
TX
RX
TX
XTAL
UA1
UA2
1
2
TMS
TRST
NC
RESET_IN
OUT2
OUT
IN
VPP_ID
OBSERVE
TCK
C
SCL
ADR
0
1
2 SDA
WC
67
2
1
J
4
7
7
32
I
2
3CD0 B2
A
4
3CDA B5
B
C
F
3CD1-2 C2
3CD1-3 C2
9CD0 D7
12
11
I
FCD8 B3
E
C
B
3
9
FCD2 B3
3CDC D6
11
4
8
9
H
1CD0 A2
3C40 C1
G
12 13
3CD1-1 C2
A
3CD9 B5
B
only for DEBUG
3CD7 B5
3CD8 B5
FCD0 B3
A
34
H
FCD6 D5
6
3CDB D7
2CD1 A2
3CD2 C2
owner.
D
C
6
F
3CD3 B2
A
8
23
ICD8 B3
3CD1-4 C1
PNX5100 : CONTROL
5
is prohibited without the written consent of the copyright
7
G
5
B
13
10
E
FCD9 D5
FCD1 B3
1
7C00-1 A3
7CD0 C4
6
5
5
C
DD
10
3CDD D6
1
FCD3 B3
FCD4 B3
D
C08 OR C16
2CD0 A2
1
J
All rights reserved. Reproduction in whole or in parts
10K
3C40
+3V3
100R
3CDD
130
9CD0
ROYAL PHILIPS ELECTRONICS N.V. 2008
69
SETNAMECHN
CLASS_NO
SUPERS.
2
NAME
DATECHECK
8204 000 8928
TV543 R2 LDIPNX
CONTROL PNX5100
A3
FCD6
32008-10-10
Maelegheer Ingrid
2008-11-21
FCD3
RES
100R3CD9
+3V3
3CD0
100R
J1
J2
AF8
AE8
AD8
AC8
AB21
AE13
AF13
AF14
R1
AF24
AD12
K2
L2
K1
L1
H4
H2
H3
CONTROL
Φ
7C00-1
PNX5100E
G22
H22
W22
Y22
27p
FCD2
2CD1
1
2
3
6
5
84
7
M24C16-WDW6
7CD0
EEPROM
Φ
(2Kx8)
FCD8
3CDA 100R
RES
+3V3
3CD1-1
10K
ICD8
1CD0
27M
+3V3
10K
3CD3
10K
10K
3CD1-2
3CD1-4
27p
2CD0
FCD0
3CDB
4K7
+3V3
FCD9
+3V3
FCD4
10K
3CD2
3CD8 100R
FCD1
+3V3
3CDC
100R
10K
3CD1-3
100R3CD7
SDA-AMBI-3V3
EJTAG-PNX5100-TDO
EJTAG-PNX5100-TCK
+3V3
RESET-PNX5100
PNX5100-RST-OUT
EJTAG-PNX5100-TRSTn
CLK-OUT-PNX5100
EJTAG-PNX5100-TDI
EJTAG-PNX5100-TMS
SCL-SSB
WC-EEPROM-PNX5100
SCL-SSB
SDA-SSB
WC-EEPROM-PNX5100
SDA-SSB
SCL-AMBI-3V3
18310_523_090302.eps
090302