Philips Q549.2E Flat Panel Television User Manual


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EN 118Q549.2E LA 10.
Circuit Diagrams and PWB Layouts
2009-May-08
SSB: FPGA WOW - I/O Banks
C
VCCD_PLL2 VCCA2
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
GNDA2
VCCD_PLL1 VCCA1
GNDA1
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCIO6
VCCIO1
VCCIO8
VCCIO5
VCCIO2
VCCIO4
VCCIO7
VCCIO3
VCCD_PLL3
GNDA3
CE
CONFIG
DCLK
STATUS
TCK
TDI
TDO
TMS
VCCA3
GND
GND
GND
GNDGND
GND
GND
GND
VCCD_PLL4 VCCA4
GNDA4
9FND C9
FF18 A1
FF19 B1
FF48 B1
IFN0 A2
P
19
IFN4 B9
IFN5 B9
IFN6 B11
IFN7 B11
IFN8 B137FN0-5 C1
7FN0-6 C5
7FN0-7 C10
7FN0-8 C13
7FN0-9 E4
9FN0 D4
IFNB B15
IFNC D13
IFND E11
IFNF D7
IFNG D5
IFNH D3
IFNJ D3
IFNK D4
IFNL D4
IFNM D5
I
5
FPGA WOW - IO-BANKS
L
155
IFNN D59FN8 D5
9FN9 D7
9FNA D7
9FNB D7
9FNC E7
3F74-3 B2
3F74-4 B5
3FN1 A1
3FN2 B1
3FN3 B1
3FNF E7 IFN1 A4
IFN2 B8
IFN3 B8
1411
O
H
6
10
B
7
A
O
13
K
IFN9 B13
IFNA B15
7FN0-2 A6
7FN0-3 A10
7FN0-4 A13
C
D
E
F
G
H
9FN1 D4
9FN4 E4
9FN6 E4
E
3
N
118
E
H
7
owner.
M
K
9FN7 E4
12
3F74-2 B4
6 7 8 9 10 11
3FNG E7
7FN0-1 A3
7FN0-10 F11
B
91
1
13 19
G
184
M
14 15
A
B
8 9 10 11 12 13
A
B
C
L
20
C
3
F
C
144
2345
2FN0 D9
2FN1 D9
2FN2 D9
2FN3 D9
2FN5 D12
2FN6 D13
12 13
17
9 18
F
16
All rights reserved. Reproduction in whole or in parts
15 20
1
D
4567
JJ
I
14
12
2 17
N
D
62
G
A
P
D
15
1
F
G
H
2F43 E7
6
+1V2-FPGA
E
2FN7 D13
8
10
is prohibited without the written consent of the copyright
23
16
3F74-3
47R
3
3FNF
100R
IFNB
TV543 R2 LDIPNX
8204 000 8933
CHECK DATE
NAME
2
SUPERS.
CLASS_NO
EMANTESNHC
87
2007-12-06
ROYAL PHILIPS ELECTRONICS N.V. 2007
2008-11-21
Maelegheer Ingrid
2008-10-10 3
130 A2
FPGA WOW - IO-BANKS
+2V5-PLL
9FN6
+1V2-PLL
IFNK
+2V5-DDR1
VREF-FPGA1
IFNG
+2V5-PLL
+1V2-FPGA
+3V3-FPGA
+1V2-FPGA
+1V2-FPGA
3FNG
100R
+3V3-FPGA
IFND
IFNA
+3V3-FPGA
IFNF
1n0
+1V2-FPGA
+1V2-FPGA
2FN0
9FN7
3FN2
10K
VREF-FPGA1
9FN8
2FN5
1n0
IFN3
+2V5out-FPGA
+2V5out-FPGA
VREF-FPGA1
+2V5in-FPGA
IFN4
1n0
2FN6
+1V2-FPGA
+1V2-FPGA
IFN2
+1V2-FPGA
IFNN
IFN0
+2V5in-FPGA
FF19
+2V5in-FPGA
9FNC
+2V5-DDR1
RES
IFNC
K13
J18
J17
J14
F14
E15
+2V5in-FPGA
IO_G18|R27N|INIT_DONE
G18
IO_H13|R8P|RDY
H13
IO_H14|R8N|AVD_
H14
IO_H15|VREFB6N1
H15
IO_H16|R23N
H16
IO_H17|R28P
H17
IO_H18|VREFB6N2
H18
IO_J13|VREFB6N3
J13
IO_C17|R5P|PADD21
C17
IO_C18|R5N|PADD22
C18
IO_D17|R12P|OE_
D17
IO_D18|R12N|WE_
D18
IO_E17|R24P|CLKUSR
E17
IO_E18|R24N|CEO_
E18
IO_G14|R7N|PADD23
G14
IO_G17|R27P|CRC_ERROR
G17
CLK4|CLK_2P
F17
CLK5|CLK_2N
F18
K14
F15
IO_B17|VREFB6N0
B17
IO_B18|R4N|PADD20
B18
7FN0-6
EP3C40F324C7N
BANK6
V5
IO_V5|B18N
V6
IO_V6|B24N
V7
IO_V7|B26N
V8
IO_V8|B27N
+2V5in-FPGA
IO_U5|B18P
U6
IO_U6|B24P
U7
IO_U7|B26P
U8
IO_U8|B27P
V1
IO_V1|B1N
V2
IO_V2|PLL1_CLKOUTN
V3
IO_V3|B16N
V4
IO_V4|B17N
IO_R8|B21P
T4
IO_T4|VREFB3N3
T6
IO_T6|VREFB3N2
T8
IO_T8|B21N
U1
IO_U1|B1P
U2
IO_U2|PLL1_CLKOUTP
U3
IO_U3|B16P
U4
IO_U4|B17P
U5
V9
CLK14|CLK_6N
U9
CLK15|CLK_6P
P6
IO_P6|B6P
P7
IO_P7|VREFB3N1
P8
IO_P8|VREFB3N0
P9
IO_P9|B23N
R8
BANK3
EP3C40F324C7N
7FN0-3
VREF-FPGA1
+1V2-FPGA
9FND
RES
VREF-FPGA1
3FN3
10K
+3V3-FPGA
VREF-FPGA1
IO_T1|RDN1
T1
IO_T2|RUP1
T2
IO_T3|L52P
T3
N5
P4
IO_M5
M5
IO_P1|L44N
P1
IO_P2|L44P
P2
IO_R1|VREFB2N2
R1
IO_R2|L45P
R2
IO_R3|L52N
R3
IO_R4
R4
IO_R5|VREFB2N3
R5
IO_L2|L32P
L2
IO_L3|L33N
L3
IO_L4|L33P
L4
IO_L5|L28N
L5
IO_L6|VREFB2N0
L6
IO_M1|L34N
M1
IO_M2|L34P
M2
IO_M3|VREFB2N1
M3
CLK2|CLK_1P
N2
CLK3|CLK_1N
N1
P5
IO_K1|L26N
K1
IO_K2|L26P
K2
IO_K5|L28P
K5
IO_L1|L32N
L1
7FN0-2
EP3C40F324C7N
BANK2
FF48
+2V5-PLL
RES9FNB
IO_D12|VREFB7N1
D12
IO_D14|PLL2_CLKOUTP
D14
IO_D16|T49P
D16
IO_E11|VREFB7N3
E11
IO_E12|T45P|PADD0
E12
IO_E13|RDN4
E13
IO_E14|RUP4
E14
IO_B14|T36P|PADD6
B14
IO_B15|T37P|PADD4
B15
IO_B16|T41P|PADD2
B16
IO_C10|T27N|PADD13
C10
IO_C12|VREFB7N2
C12
IO_C14|PLL2_CLKOUTN
C14
IO_C16|T49N
C16
IO_D10|T27P|PADD14
D10
A14
IO_A15|T38N|PADD3
A15
IO_A16|T41N|PADD1
A16
IO_A17|VREFB7N0
A17
IO_A18|T48P
A18
IO_B11|T29P|PADD12
B11
IO_B12|T31P|PADD10
B12
IO_B13|T35P|PADD8
B13
CLK8|CLK_5N
A10
CLK9|CLK_5P
B10
IO_A11|T29N|PADD11
A11
IO_A12|T31N|PADD9
A12
IO_A13|T35N|PADD7
A13
IO_A14|T36N|PADD5
7FN0-7
EP3C40F324C7N
BANK7
+1V2-FPGA
E6
IO_E6|VREFB8N3
E7
IO_E7|T5N|DATA9
E8
IO_E8|T8P|DATA6
E9
IO_E9|VREFB8N0
IFNJ
B8
IO_B8|T20P|DATA3
C5
IO_C5|T11P|DATA5
C7
IO_C7|VREFB8N1
C9
IO_C9|T24N|PADD16
D5
IO_D5|T3P|DATA12
D7
IO_D7|VREFB8N2
D9
IO_D9|T24P|PADD17
E10
IO_E10|T25P|PADD15
A6
IO_A6|T18N|PADD19
A7
IO_A7|T19N|PADD18
A8
IO_A8|T20N|DATA2
B3
IO_B3|T4P|DATA11
B4
IO_B4|T6P|DATA8
B5
IO_B5|T16P|DATA13
B6
IO_B6|T18P|DATA15
B7
IO_B7|T19P|DATA4
A9
CLK10|CLK_4N
B9
CLK11|CLK_4P
A1
IO_A1|PLL3_CLKOUTN
A2
IO_A2|PLL3_CLKOUTP
A3
IO_A3|T4N|DATA10
A4
IO_A4|T7N|DATA7
A5
IO_A5|T16N|DATA14
7FN0-8
EP3C40F324C7N
BANK8
V15
IO_V15|B35N
V16
IO_V16|B44N
V17
IO_V17|B47N
V18
IO_V18|PLL4_CLKOUTN
U15
IO_U15|B35P
U16
IO_U16|VREFB4N1
U17
IO_U17|B47P
U18
IO_U18|PLL4_CLKOUTP
V11
IO_V11|B28N
V12
IO_V12|VREFB4N3
V13
IO_V13|B32N
V14
IO_V14|B34N
R13
IO_R13|B48N
T11
IO_T11|VREFB4N2
T13
IO_T13|RUP2
T14
IO_T14|RDN2
U11
IO_U11|B28P
U12
IO_U12|B29P
U13
IO_U13|B32P
U14
IO_U14|B34P
V10
CLK12|CLK_7N
U10
CLK13|CLK_7P
P10
IO_P10|B33P
P11
IO_P11|B33N
P12
IO_P12
P13
IO_P13|VREFB4N0
R11
IO_R11|B36N
BANK4
EP3C40F324C7N
7FN0-4
+3V3-FPGA
+1V2-FPGA
VREF-FPGA1
IFN8
+1V2-FPGA
RES
9FN9
VREF-FPGA1
+3V3-FPGA
2FN1
+2V5out-FPGA
+1V2-FPGA
+2V5-DDR1
1n0
+1V2-PLL
IFN1
IFN7
+1V2-FPGA
1n0
2FN3
+1V2-FPGA
9FNA
IFNM
+2V5out-FPGA
+1V2-PLL
RES
3FN1 1K0
+1V2-FPGA
9FN0 RES
+1V2-FPGA
9FN4
+3V3-FPGA
FF18
+2V5out-FPGA
3F74-2
47R
2
7
IFN6
+1V2-FPGA
+3V3-FPGA
IFNL
+3V3-FPGA
IFN5
IFN9
+1V2-FPGA
2FN7
1n0
+1V2-FPGA
IFNH
G5
J1
J6
J5
J2
E4
F5
IO_E2|L10P|FLASH_CE_|CSO_
E2
IO_F3|VREFB1N1
F3
IO_G1|L20N
G1
IO_G2|L20P
G2
IO_H1|VREFB1N3
H1
IO_H2
H2
IO_H3|DATA0
H3
IO_H6|VREFB1N2
H6
IO_B2|L1P
B2
IO_C1|L3N
C1
IO_C2|VREFB1N0
C2
IO_C3|L4P|RESET_
C3
IO_D1|L8N|DATA1|ASDO
D1
IO_D2|L8P
D2
IO_D3|L7P
D3
IO_E1|L10N
E1
K6
CLK0|CLK_0P
F2
CLK1|CLK_0N
F1
H5
H4
E5
IO_B1|L1N
B1
+1V2-FPGA
7FN0-1
EP3C40F324C7N
BANK1
47R
4
5
D8
+1V2-FPGA
3F74-4
K15
M15
R15
F16
G15
J15
D11
D13
D15
D4
D6
J4
K4
M4
N4
R6
R7
R9
R10
R12
R14
N7
N9
F6
F8
G10
G11
G12
G13
G7
F4
G4
L12
L7
M11
F12
M12
M6
M7
M8
M9
N11
N13
F10
G8
H12
H7
J12
J7
K12
K7
7FN0-9
EP3C40F324C7N
VCC
2F43
1n0
+1V2-FPGA
9FN1
+2V5out-FPGA
+2V5-PLL
1n0
+1V2-FPGA
+2V5-DDR1
+2V5in-FPGA
2FN2
IO_R16|RDN3
IO_R17|VREFB5N2
R17
IO_R18|VREFB5N3
R18
IO_T16|RUP3
T16
IO_T17|R54N
T17
IO_T18
T18
N14
P15
IO_L18|VREFB5N0
IO_M14|R38N
M14
IO_M17|R33N
M17
IO_M18|R32N|DEV_OE
M18
IO_N15|R55P
N15
IO_N16|VREFB5N1
N16
IO_P17|R42P
P17
IO_P18|R42N
P18
R16
P14
IO_K17|R29P
K17
IO_K18|R29N
K18
IO_L13|R38P
L13
IO_L14|R36P
L14
IO_L15|R36N
L15
IO_L16|R33P
L16
IO_L17|R32P|DEV_CLR_
L17
L18
BANK5
CLK6|CLK_3P
N17
CLK7|CLK_3N
N18
+1V2-FPGA
7FN0-5
EP3C40F324C7N
+1V2-FPGA
+1V2-FPGA
+1V2-PLL
T9
C13
T10
T12
T15
C15
E3
E16
F7
M16
C11
N3
N6
N8
N10
N12
P3
P16
T5
T7
K9C8
K10
K11
K16
L8
L9
L10
L11
M10
M13
C6
H11
J3
J8
J9
J10
J11
J16
K3
K8
C4
F9
F11
F13
G3
G6
G9
G16
H8
H9
H10
7FN0-10
EP3C40F324C7N
GND
ASDO
nCSO
nSTATUS
MSEL2
MSEL1
MSEL3
+2V5-DDR1
+2V5-DDR1
TX851CLK-
TX851CLK+
CLK-OUT2-PNX5100
CLK-OUT-PNX5100
TX851B+
TX851B- MM1-A2
MM1-A4
TX851D-
TX851B+
TX851C+
TX851A-
TX851A+
TX851D+
TX851E-
TX851E+
TX851C-
nCONFIG
nCE
MSEL0
CLK-OUT2-PNX5100
SCL-AMBI-3V3
SDA-AMBI-3V3
BACKLIGHT-OUT
BACKLIGHT-CONTROL-FPGA-IN
SDA-SSB
SCL-SSB
DCLK
TMS
nCE
nCONFIG
nSTATUS
TCK
TDI
TDO
MM1-A6
MM1-D15
MM1-D11
MM1-A5
MM1-D9
MM1-D14
MM1-A8 MM1-DQS0
MM1-D10
MM1-D12
MM1-D13
MM1-A12
MM1-A11
MM1-A9
MM1-A7
MM1-BA1
MM1-BA0
MM1-CLK-
MM1-CLK+
MM1-CKE
MM1-D8
MM1-DQS1
MM1-D4
MM1-RAS
MM1-D6
MM1-A3
MM1-WE
MM1-A1
MM1-D0
MM1-D5
MM1-CAS
MM1-D7
MM1-A0
MM1-A10
MM1-D2
CON23
CON22
CON21
CON20
MM1-D1
MM1-CS0
MM1-D3
TX852D-
TX852C-
TX852B-
TX852A-
CONF-DONE
BACKLIGHT-OUT2
CON27
CON26
TX852E+
TX852D+
TX852C+
TX852B+
TX852A+
TX852E-
TXF2B-
TXF2C-
TXF2CLK-
TXF2D-
TXF2E-
TX852CLK-
TX852CLK+
TXF2A+
TXF2B+
TXF2C+
TXF2CLK+
TXF2D+
TXF2E+
TXF2A-
TXF1CLK-
TXF1CLK+
TXF1D-
TXF1D+
TXF1E-
TXF1E+
DATA0
TXF1A-
TXF1A+
TXF1B-
TXF1B+
TXF1C-
TXF1C+
18310_533_090303.eps
090303
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